mirror of https://github.com/openXC7/prjxray.git
36 lines
1.1 KiB
Markdown
36 lines
1.1 KiB
Markdown
Timing minitest
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===============
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This minitest uses Vivado to compile a design and extracts the relevant timing
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metadata from the design, e.g. what are the nets and how was the design routed.
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For each clock path, the final timing is provided for each of the 4 corners of
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analysis.
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From the timing metadata, ``create_timing_worksheet_db.py`` creates a worksheet
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breaking down the interconnect timing calculation and generating a final
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comparision between the reduced model implemented in prjxray and the Vivado
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timing results.
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Model quality
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-------------
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The prjxray timing handles most nets +/- 1.5% delay. The large exception to
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this is clock nets, which appear to use a table lookup that is not understood
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at this time.
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Running the model
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-----------------
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The provided Makefile will by default compile all examples. It a specific design
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family is desired, the family name can be provided. If a specific design within
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a family is desired, use ``<family name>_<iter>``.
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Example:
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```
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# Build all variants of the DFF loopback test
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make dff
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# Build only DESIGN_NAME=dff ITER=63
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make dff_63
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```
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