mirror of https://github.com/openXC7/prjxray.git
125 lines
3.0 KiB
Markdown
125 lines
3.0 KiB
Markdown
# ROI_HARNESS Minitest
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## Purpose
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Creates an harness bitstream which maps peripherals into a region of interest
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which can be reconfigured.
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The currently supported boards are;
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* Artix 7 boards;
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- [Basys 3](https://github.com/SymbiFlow/prjxray-db/tree/master/artix7/harness#basys-3)
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- [Arty A7-35T](https://github.com/SymbiFlow/prjxray-db/tree/master/artix7/harness#arty-a7-35t)
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* Zynq boards;
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- [Zybo Z7-10](https://github.com/SymbiFlow/prjxray-db/tree/master/zynq7/harness#zybo-z7-10)
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The following configurations are supported;
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* SWBUT - Harness which maps a board's switches, buttons and LEDs into the
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region of interest (plus clock).
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* PMOD - Harness which maps a board's PMOD connectors into the region of
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interest (plus a clock).
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* UART - Harness which maps a board's UART
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"ARTY-A7-SWBUT"
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# 4 switches then 4 buttons
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A8 C11 C10 A10 D9 C9 B9 B8
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# 4 LEDs then 4 RGB LEDs (green only)
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H5 J5 T9 T10 F6 J4 J2 H6
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# clock
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E3
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"ARTY-A7-PMOD"
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# CLK on Pmod JA
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G13 B11 A11 D12 D13 B18 A18 K16
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# DIN on Pmod JB
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E15 E16 D15 C15 J17 J18 K15 J15
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# DOUT on Pmod JC
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U12 V12 V10 V11 U14 V14 T13 U13
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"ARTY-A7-UART"
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# RST button and UART_RX
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C2 A9
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# LD7 and UART_TX
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T10 D10
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# 100 MHz CLK onboard
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E3
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"BASYS3-SWBUT"
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# Slide switch pins
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V17 V16 W16 W17 W15 V15 W14 W13 V2 T3 T2 R3 W2 U1 T1 R2
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# LEDs pins
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U16 E19 U19 V19 W18 U15 U14 V14 V13 V3 W3 U3 P3 N3 P1 L1
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# UART
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B18 # ins
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A18 # outs
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# 100 MHz CLK onboard
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W5
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"ZYBOZ7-SWBUT"
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# J15 - UART_RX - JE3
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# G15 - SW0
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# K18 - BTN0
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# K19 - BTN1
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J15 G15 K18 K19
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# H15 - UART_TX - JE4
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# E17 - ETH PHY reset (active low, keep high for 125 MHz clock)
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# M14 - LD0
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# G14 - LD2
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# M15 - LD1
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# D18 - LD3
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# 125 MHz CLK onboard
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K17
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## Quickstart
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```
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source settings/artix7.sh
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cd minitests/roi_harness
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source arty-swbut.sh
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make clean
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make copy
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```
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## How it works
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Basic idea:
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- LOC LUTs in the ROI to terminate input and output routing
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- Let Vivado LOC the rest of the logic
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- Manually route signals in and out of the ROI enough to avoid routing loops into the ROI
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- Let Vivado finish the rest of the routes
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There is no logic outside of the ROI in order to keep IOB to ROI delays short
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Its expected the end user will rip out everything inside the ROI
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To target Arty A7 you should source the artix DB environment script then source arty.sh
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To build the baseline harness:
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```
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./runme.sh
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```
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To build a sample Vivado design using the harness:
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```
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XRAY_ROIV=roi_inv.v XRAY_FIXED_XDC=out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/fixed_noclk.xdc ./runme.sh
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```
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Note: this was intended for verification only and not as an end user flow (they should use SymbiFlow)
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To use the harness for the basys3 demo, do something like:
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```
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python3 demo_sw_led.py out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev 3 2
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```
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This example connects switch 3 to LED 2
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## Result
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