mirror of https://github.com/openXC7/prjxray.git
24 lines
726 B
Markdown
24 lines
726 B
Markdown
# PLLE2_ADV minitest
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## Description
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This test verifies operation of the `PLLE2_ADV` primitive. The PLL is configured to output clocks using the following dividers:
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- CLKOUT0: 16/16
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- CLKOUT1: 16/32
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- CLKOUT2: 16/48
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- CLKOUT3: 16/64
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- CLKOUT4: 16/80
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- CLKOUT5: 16/96
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The input clock can be swtched between 100MHz and 50MHz using the `sw[1]` switch. The 50MHz clock is generated using simple divider implemented in logic.
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Clocks from the PLL are further divided by 2^21 and then fed to LEDs 0:5. PLL lock indicator is connected to LED 15. The switch `sw[0]` provides reset signal to the PLL.
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## Building
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To build the project run the following command and the bit file will be generated.
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```
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make basys3_plle2_adv.bit
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```
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