mirror of https://github.com/openXC7/prjxray.git
34 lines
1.5 KiB
Markdown
34 lines
1.5 KiB
Markdown
# FASM Proof of Concept using Vivado Partial Reconfig flow
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harness.v is a top-level design that routes a variety of signal into a black-box
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region of interest (ROI). Vivado's Partial Reconfiguration flow (see UG909
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and UG947) is used to implement that design and obtain a bitstream that
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configures portions of the chip that are currently undocumented.
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Designs that fit within the ROI are written in FASM and merged with the above
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harness into a bitstream with fasm2frame and xc7patch. Since writting FASM is
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rather tedious, rules are provided to convert Verilog ROI designs into FASM via
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Vivado.
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## Usage
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make rules are provided for generating each step of the process so that
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intermediate forms can be analyzed. Assuming you have a .fasm file, invoking
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the %\_hand\_crafted.bit rule will generate a merged bitstream:
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```
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make foo.hand\_crafted.bit # reads foo.fasm
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```
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## Using Vivado to generate .fasm
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Vivado's Partial Reconfiguration flow can be used to synthesize and implement a
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ROI design that is then converted to .fasm. Write a Verilog module
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that _exactly_ matches the roi blackbox model in the top-level design. Note
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that even the name of the module must match exactly. Assuming you have created
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that design in my\_roi\_design.v, 'make my\_roi\_design\_hand\_crafted.bit'
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will synthesize and implement the design with Vivado, translate the resulting
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partial bitstream into FASM, and then generate a full bitstream by patching the
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harness bitstream with the FASM. non\_inv.v is provided as an example ROI
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design for this flow.
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