mirror of https://github.com/openXC7/prjxray.git
28 lines
1.3 KiB
Markdown
28 lines
1.3 KiB
Markdown
LitePCIe minitest
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=================
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This minitest is intended to provide a counter-prove on the possible remaining features to document for
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the Gigabit Transcievers (GTP tiles) and the PCIE\_2\_1 primitive.
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It uses the following litex modules:
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| Repo URL | SHA |
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| --------------------------------------------------------- | ------- |
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| <https://github.com/enjoy-digital/litex> | 7abfbd9 |
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| <https://github.com/enjoy-digital/litedram> | ab2423e |
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| <https://github.com/enjoy-digital/liteeth> | 7448170 |
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| <https://github.com/enjoy-digital/liteiclink> | 0980a7c |
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| <https://github.com/enjoy-digital/litepcie> | 1d7b584 |
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| <https://github.com/enjoy-digital/litex-boards> | 1d8f0a9 |
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| <https://github.com/m-labs/migen> | 40b1092 |
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| <https://github.com/nmigen/nmigen> | 490fca5 |
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| <https://github.com/litex-hub/pythondata-cpu-vexriscv> | 16c5dde |
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The final FASM file with the `unknown bits` can be obtained by running the following:
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```bash
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make all
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```
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All the pre-requisites (LiteX, RISC-V toolchain, etc.) are automatically installed/built. It is required though to have Vivado installed in the system.
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