Both fuzzers crashed in Vivado with 'ERROR: [Common 17-69] Missing
name/value pair in -dict argument' at the set_property -dict 'LOC ...
BEL ...' line. Cause: generate.tcl reserves 3*todo_lines INT tiles
via randsample_list (utils.tcl), which samples without replacement
and pads with empty strings once exhausted. The off-edge virtex7 ROI
holds only ~150 INT_L/INT_R tiles, but 053 has 64 todo lines, so
3*64=192 > 150 and the tail of the sample is empty entries; high-idx
todo lines (tile_idx = idx*3) get empty tiles -> empty driver_site
-> odd-length -dict -> error.
Reduce the per-todo-line retry window from 3 to 2 (set tiles
expr 2*todo_lines, tile_idx idx*2, retry limit tries>=2). 2*64=128
fits comfortably in ~150 pool. Other pip fuzzers use a different
indexing pattern; only these two use idx*K. For larger-ROI families
the pool still exceeds 2*N as it did 3*N, so no regression.
Verified: 053 single-specimen run reaches all 64 todo lines (idx 63
previously died at 50), emits segdata_int_l/r; 055 likewise.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting
xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families.
Family registration:
- settings/virtex7.sh, settings/virtex7/devices.yaml
- Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets
- utils/update_parts.py, update_resources.py: virtex7 choice
- CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README
Architecture adaptations for the HP-bank-only VX part (verified non-breaking):
- update_resources.tcl: fall back to HP banks when no HR banks exist
- XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised
across the fuzzer generate.tcl files
- fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7;
GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads)
- 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2;
ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles;
per-specimen retry for transient FlexLM SIGSEGV under concurrency
- per-family Vivado version gate (virtex7 -> v2020.1.1)
- XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region
General fixes:
- tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the
larger Virtex-7 bitstream)
- utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable
install doesn't expose the repo-root utils/ package)
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
* Make sure all files have top level headers.
* Fixing a few spelling mistakes.
* Fixed some trailing spaces.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
Dr Jonathan Richard Robert Kimmitt
Tomasz Michalak
Tim 'mithro' Ansell
Keith Rothman
John McMaster