luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,279 Commits 31 Branches 4 Tags 7.7 MiB
Commit Graph

930 Commits

Author SHA1 Message Date
Tim Ansell bb8640bda9
Merge pull request #880 from litghost/add_back_hclk_ppips 
Add HCLK ppips.
 2019-06-12 09:29:18 +02:00
litghost d31319ccaa
Merge pull request #879 from litghost/avoid_full_dict_build 
Avoid building full speed_model dict.
 2019-06-11 14:59:41 -07:00
Keith Rothman aeaa8a3530 Add HCLK ppips. 
These were no longer generated after 946892d1b and were removed from
prjxray-db at
b13ff7f8b3 (diff-6a43cc2ab2e06b2a84b7effc16ca669e)

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-11 14:58:15 -07:00
Keith Rothman 2ad76619ee Avoid building full speed_model dict. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-11 10:32:24 -07:00
Tomasz Michalak 6fb68593ff 059-pip-byp-bounce: Add separate fuzzer for FAN_ALT.BYP_BOUNCE bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-05 19:26:07 +02:00
Tomasz Michalak 14efe4d720 050-pip-seed: Don't solve FAN_ALT.BYP_BOUNCE bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-05 08:24:11 +02:00
litghost 71970f9b38
Merge pull request #849 from antmicro/prjxray_stabilization_053_pip_ctrlin 
053-pip-ctrlin: Fall back to todos bigger than specified number of lines
 2019-06-04 09:35:53 -07:00
Tomasz Michalak 369362f8c8 005-tilegrid: add CFG_CENTER_MID tile base address calculation 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-31 09:40:40 +02:00
litghost 0bddcaf908
Merge pull request #858 from litghost/timing_fuzzer 
Add wire, pip, and site pin timing information.
 2019-05-30 18:20:43 -07:00
litghost 84e168c9dc
Merge pull request #831 from antmicro/prjxray_stabilization_057_pip_bi 
057-pip-bi: Increase number of tries to find a suitable PIP INT tile
 2019-05-30 12:17:02 -07:00
Keith Rothman 0dc1317389 Add comment on magic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-30 09:18:47 -07:00
Keith Rothman e1208e1014 Add wire, pip, and site pin timing information. 
This is required for interconnect timing modelling.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-29 14:51:35 -07:00
Tomasz Michalak ebf8d6a1cd 053-pip-ctrlin: Fall back to todos bigger than specified number of lines 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-29 08:35:08 +02:00
litghost e8299f6404
Merge pull request #842 from antmicro/bits_origin 
Generate db files with fuzzer name of origin
 2019-05-28 09:57:08 -07:00
Tomasz Michalak 22cdae1536 Generate db files with fuzzer name of origin 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-27 08:46:44 +02:00
Tim Ansell ff4c80738d
Merge pull request #850 from antmicro/fuzzer_007_python3 
Make build scripts of 007 explicitly use python3
 2019-05-25 15:21:03 -07:00
Maciej Kurc 306b40eebb Changed all scripts to use explicitly python3 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-24 15:05:53 +02:00
Tomasz Michalak 86057f3d17 018-clb-ram: Increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-24 08:05:41 +02:00
Tomasz Michalak efb0b14b3a 057-pip-bi: Increase try count limit 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-24 08:02:58 +02:00
Tomasz Michalak 11f5a37a06 050-pip-seed: Increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-23 20:49:14 +02:00
Tomasz Michalak 58baff4f4a fuzzers: Add clean_piplists target 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-23 15:19:16 +02:00
Karol Gugala 683b7562e5 fuzzer: 007: bel: handle multiple bit inputs 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-16 19:14:35 +02:00
Karol Gugala e1440a56b4 fuzzers: 007: add properties names mappings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-16 14:52:58 +02:00
Karol Gugala 788e3e0855 fuzzers: 007: correctly handle input clocks and extended pin names 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-14 17:34:07 -07:00
Tomasz Michalak e7ce84abbe
Merge pull request #822 from antmicro/prjxray_stabilization_045_hclk_cmt_pips 
045-hclk-cmt-pips: account for hclk_cmt tiles missing from zynq7 and …
 2019-05-14 11:52:47 +02:00
Tomasz Michalak c4e062fa6e 053-pip-ctrlin: increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-13 22:25:43 +02:00
Tomasz Michalak fe809d7d0d 045-hclk-cmt-pips: increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-13 10:17:35 +02:00
Tomasz Michalak 7e05327c97 056-pip-rem: Delete net and cell after unsuccessful routing attempt 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-10 11:14:10 +02:00
Tomasz Michalak b5a4e6932e run_fuzzer.py: Adjust unit names output by free tool 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-09 09:33:22 +02:00
Tim 'mithro' Ansell fbec529926 Less verbose memory usage info. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-05-08 10:09:45 +02:00
Tim 'mithro' Ansell 1ca3f55b05 Fix doctest for Logger. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-05-08 10:09:45 +02:00
Tomasz Michalak 64c0a3c0b4
Merge pull request #824 from antmicro/043-clk-rebuf-pips-zynq 
Resolve missing CLK_REBUF PIPs bits for Zynq
 2019-05-08 07:55:02 +02:00
Tomasz Michalak af50a5f32a 043-clk-rebuf-pips: increase the number of specimen 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 15:58:53 +02:00
Tomasz Michalak c094640034 030-iob: don't create liob segbits file for zynq 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 13:53:17 +02:00
Tomasz Michalak 9bf9d4e0fd 030-iob: skip broken tile for zynq 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 13:36:50 +02:00
Tomasz Michalak 845a8914b3 045-hclk-cmt-pips: account for hclk_cmt tiles missing from zynq7 and re-enable fuzzer 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 08:34:18 +02:00
Tim Ansell 938f3788e8
Merge pull request #706 from antmicro/bel-timing 
fuzzers: Adding BEL timing fuzzer
 2019-04-29 09:16:18 -07:00
Tomasz Michalak c91ca7cf7f 054-pip-fan-alt: add solution of BYP_ALT.GFAN PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-29 08:05:08 +02:00
Tim 'mithro' Ansell 4473789694 fuzzers: Disable timing fuzzer on Kintex. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-04-28 18:53:51 -07:00
Karol Gugala 1952b3df75 fuzzers: 007: create run.ok file 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 634ca791c7 fuzzers: 007: bel: merge slicel and slicem timigs 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 7154cfcf61 fuzzers: add timing fuzzer to global makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 69cc63ea81 utils: add sdfmerge tool 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala ba62b6b9c9 fuzzers: 007: add BEL to Makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 5d9da26f78 Fuzzers: 007: add bel timing fuzzer 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Tomasz Michalak 40f0ef6fa8 052-pip-clkin: run make format 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak d67cb4c250 052-pip-clkin: re-enable fuzzer 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak 8a47473bd1 052-pip-clkin: don't route PIPs with same wires in one run 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak 6337cac12a 052-pip-clkin: use interconnect tiles with different x coordinates 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak 28729661ac fuzzers: disable 056-pip-rem until other instabilities are fixed 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-24 07:53:48 +02:00