mirror of https://github.com/openXC7/prjxray.git
Added solution for some MMCM compensation settings
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
780b7e4d09
commit
fe82e0f281
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@ -22,14 +22,16 @@ def bitfilter(frame, word):
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return True
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def bus_tags(segmk, ps, site):
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def bus_tags(segmk, ps, all_params, site):
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segmk.add_site_tag(site, 'IN_USE', ps['active'])
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if not ps['active']:
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return
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for k in ps:
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segmk.add_site_tag(site, 'param_' + k + '_' + str(ps[k]), 1)
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params = all_params[site]["params"]
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#for k in ps:
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# segmk.add_site_tag(site, 'param_' + k + '_' + str(ps[k]), 1)
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for reg, invert in [
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('RST', 1),
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@ -51,86 +53,15 @@ def bus_tags(segmk, ps, site):
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elif verilog.unquote(ps['BANDWIDTH']) == 'LOW':
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segmk.add_site_tag(site, 'BANDWIDTH.' + opt, 0)
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for opt in ['ZHOLD', 'BUF_IN', 'EXTERNAL', 'INTERNAL']:
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continue
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# "INTERNAL" compensation conflicts with the CLKFBOUT2IN->CLKFBIN PIP.
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# There is no telling which of these two is actually controlled by those
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# bits. It is better to leave them for the PIP.
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COMPENSATION_OPTS = ['ZHOLD', 'BUF_IN', 'EXTERNAL']
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opt_match = verilog.unquote(ps['COMPENSATION']) == opt
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if ps['clkfbin_conn'] == '':
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segmk.add_site_tag(site, 'COMP.NOFB_' + opt, opt_match)
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segmk.add_site_tag(site, 'COMP.ZNOFB_' + opt, opt_match)
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continue
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for conn in ['clk', 'clkfbout_mult_BUFG_' + ps['site'],
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'clkfbout_mult_' + ps['site']]:
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conn_match = ps['clkfbin_conn'] == conn
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segmk.add_site_tag(
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site, 'COMP.' + opt + '_' + conn + '_' + ps['site'], opt_match
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and conn_match)
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segmk.add_site_tag(
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site, 'COMP.Z' + opt + '_' + conn + '_' + ps['site'],
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not opt_match and conn_match)
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segmk.add_site_tag(
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site, 'COMP.Z' + opt + '_Z' + conn + '_' + ps['site'],
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not opt_match and not conn_match)
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segmk.add_site_tag(
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site, 'COMP.' + opt + '_Z' + conn + '_' + ps['site'], opt_match
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and not conn_match)
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#bufg_on_clkin = \
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# 'BUFG' in ps['clkin1_conn'] or \
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# 'BUFG' in ps['clkin2_conn']
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# This one is in conflict with some clock routing bits.
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# match = verilog.unquote(ps['COMPENSATION']) in ['BUF_IN', 'EXTERNAL']
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# if not match:
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# if verilog.unquote(ps['COMPENSATION']) == 'ZHOLD' and bufg_on_clkin:
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# match = True
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# segmk.add_site_tag(
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# site, 'COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF', match)
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#match = verilog.unquote(ps['COMPENSATION']) in ['ZHOLD']
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#segmk.add_site_tag(
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# site, 'COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF', not match
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# or (match and bufg_on_clkin))
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#segmk.add_site_tag(
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# site, 'COMPENSATION.ZHOLD_NO_CLKIN_BUF', match and \
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# not bufg_on_clkin
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# )
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#segmk.add_site_tag(
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# site, 'COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP', match and \
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# not bufg_on_clkin and \
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# site != "PLLE2_ADV_X0Y3" and site != "PLLE2_ADV_X0Y0"
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# )
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#segmk.add_site_tag(
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# site, 'COMP.ZHOLD_NO_CLKIN_BUF_TOP', match and \
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# not bufg_on_clkin and \
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# (site == "PLLE2_ADV_X0Y3" or site == "PLLE2_ADV_X0Y0")
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# )
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# No INTERNAL as it has conflicting bits
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#for opt in ['ZHOLD', 'BUF_IN', 'EXTERNAL']:
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# if opt in ['BUF_IN', 'EXTERNAL']:
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# if ps['clkfbin_conn'] not in ['', 'clk']:
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# continue
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#
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# if site == "PLLE2_ADV_X0Y2" and opt == 'ZHOLD':
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# segmk.add_site_tag(
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# site, 'TOP.COMPENSATION.' + opt,
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# verilog.unquote(ps['COMPENSATION']) == opt)
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# else:
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# segmk.add_site_tag(
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# site, 'COMPENSATION.' + opt,
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# verilog.unquote(ps['COMPENSATION']) == opt)
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# segmk.add_site_tag(
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# site, 'COMPENSATION.Z_' + opt,
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# verilog.unquote(ps['COMPENSATION']) != opt)
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# This one has bits that are in conflict with clock routing
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# segmk.add_site_tag(
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# site, 'COMPENSATION.INTERNAL',
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# verilog.unquote(ps['COMPENSATION']) in ['INTERNAL'])
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for opt in COMPENSATION_OPTS:
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val = params["COMPENSATION"] == opt
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segmk.add_site_tag(site, "COMP.{}".format(opt), val)
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segmk.add_site_tag(site, "COMP.Z_{}".format(opt), not val)
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opt = (verilog.unquote(ps["SS_EN"]) == "TRUE")
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segmk.add_site_tag(site, "SS_EN", opt)
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@ -178,12 +109,17 @@ def run():
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segmk = Segmaker("design.bits")
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print("Loading params")
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f = open("params.json")
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params = json.load(f)
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params = {p["site"]: p for p in params}
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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bus_tags(segmk, j, j['site'])
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bus_tags(segmk, j, params, j['site'])
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -101,16 +101,27 @@ write_bitstream -force design.bit
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set fp [open params.json "w"]
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puts $fp "\["
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foreach cell [get_cells -hierarchical -filter {REF_NAME == MMCME2_ADV}] {
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set cells [get_cells -hierarchical -filter {REF_NAME == MMCME2_ADV}]
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set i [llength $cells]
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foreach cell $cells {
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puts $fp " {"
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puts $fp " \"tile\": \"[get_tiles -of [get_sites -of $cell]]\","
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puts $fp " \"site\": \"[get_sites -of $cell]\","
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puts $fp " \"params\": {"
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foreach prop [list_property $cell] {
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puts $fp " \"$prop\": \"[get_property $prop $cell]\","
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set props [list_property $cell]
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set j [llength $props]
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foreach prop $props {
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set str " \"$prop\": \"[get_property $prop $cell]\""
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incr j -1
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if {$j != 0} {append str ","}
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puts $fp $str
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}
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puts $fp " }"
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puts $fp " },"
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set str " }"
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incr i -1
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if {$i != 0} {append str ","}
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puts $fp $str
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}
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puts $fp "\]"
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