mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1483 from antmicro/mmcm_bit_conflict_fix
The db looks good. Merging.
This commit is contained in:
Maciej Kurc
GitHub
commit
780b7e4d09
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@ -35,6 +35,8 @@ def bus_tags(segmk, ps, site):
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('RST', 1),
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('PWRDWN', 1),
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('CLKINSEL', 0),
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('PSEN', 1),
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('PSINCDEC', 1),
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]:
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opt = 'IS_{}_INVERTED'.format(reg)
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@ -130,6 +132,9 @@ def bus_tags(segmk, ps, site):
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# site, 'COMPENSATION.INTERNAL',
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# verilog.unquote(ps['COMPENSATION']) in ['INTERNAL'])
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opt = (verilog.unquote(ps["SS_EN"]) == "TRUE")
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segmk.add_site_tag(site, "SS_EN", opt)
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for param in ['CLKFBOUT_MULT_F']:
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paramadj = int(ps[param])
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bitstr = [int(x) for x in "{0:09b}".format(paramadj)[::-1]]
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@ -21,7 +21,7 @@ proc make_manual_routes {filename} {
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# Parse the line
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set fields [split $line " "]
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set net_name [lindex $fields 0]
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set wire_name [lindex $fields 1]
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set wire_names [lrange $fields 1 end]
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# Check if that net exist
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if {[get_nets $net_name] eq ""} {
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@ -30,7 +30,7 @@ proc make_manual_routes {filename} {
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}
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# Make the route
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set status [route_via $net_name [list $wire_name] 0]
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set status [route_via $net_name $wire_names 0]
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# Failure, skip manual routing of this net
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if { $status != 1 } {
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@ -80,7 +80,7 @@ write_checkpoint -force design_pre_route.dcp
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route_design -directive Quick -preserve
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set unrouted_nets [get_nets -filter {ROUTE_STATUS!="ROUTED"}]
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set unrouted_nets [get_nets -filter {ROUTE_STATUS!="ROUTED" && ROUTE_STATUS!="INTRASITE"}]
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if {[llength $unrouted_nets] ne 0} {
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puts "MANROUTE: Got unrouted nets: $unrouted_nets"
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puts "MANROUTE: Ripping up and starting again with no fixed routes"
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@ -17,6 +17,20 @@ from prjxray.db import Database
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import json
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def find_hclk_ref_wires_for_mmcm(grid, loc):
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tilename = grid.tilename_at_loc((loc[0], loc[1] - 17))
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gridinfo = grid.gridinfo_at_tilename(tilename)
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assert gridinfo.tile_type in ['HCLK_CMT_L', 'HCLK_CMT']
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# HCLK_CMT_MUX_OUT_FREQ_REF[0-3]
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wires = []
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for idx in range(4):
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wires.append('{}/HCLK_CMT_MUX_OUT_FREQ_REF{}'.format(tilename, idx))
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return wires
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def gen_sites():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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@ -28,7 +42,15 @@ def gen_sites():
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['MMCME2_ADV']:
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yield tile_name, tile_type, site_name
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hclk_wires = find_hclk_ref_wires_for_mmcm(grid, loc)
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yield tile_name, tile_type, site_name, hclk_wires
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def gen_true_false(p):
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if random.random() <= p:
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return verilog.quote("TRUE")
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else:
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return verilog.quote("FALSE")
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def main():
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@ -53,11 +75,8 @@ module top(
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LUT1 dummy();
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""".format(N=max_sites - 1))
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for i, (
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tile_name,
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tile_type,
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site,
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) in enumerate(sorted(gen_sites())):
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for i, (tile_name, tile_type, site,
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hclk_wires) in enumerate(sorted(gen_sites())):
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params = {
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"site":
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site,
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@ -100,6 +119,10 @@ module top(
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random.randint(0, 1),
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"IS_CLKINSEL_INVERTED":
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random.randint(0, 1),
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"IS_PSEN_INVERTED":
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random.randint(0, 1),
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"IS_PSINCDEC_INVERTED":
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random.randint(0, 1),
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"CLKFBOUT_MULT_F":
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random.randint(2, 4),
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"CLKOUT0_DIVIDE_F":
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@ -136,8 +159,14 @@ module top(
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'HIGH',
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'LOW',
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))),
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"SS_EN":
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gen_true_false(0.15),
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}
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# SS_EN requires BANDWIDTH to be LOW
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if verilog.unquote(params["SS_EN"]) == "TRUE":
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params["BANDWIDTH"] = verilog.quote("LOW")
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if verilog.unquote(params['COMPENSATION']) == 'ZHOLD':
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params['clkfbin_conn'] = random.choice(
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(
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@ -154,35 +183,30 @@ module top(
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params['clkfbin_conn'] = random.choice(
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("", "clkfb[{}]".format(i), "clkfbout_mult_BUFG_" + site))
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params['clkin1_route'] = random.choice(
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(
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"{}_CLKIN1",
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"{}_FREQ_BB0",
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"{}_FREQ_BB1",
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"{}_FREQ_BB2",
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"{}_FREQ_BB3",
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"{}_MMCME2_CLK_IN1_INT",
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)).format(tile_type)
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def get_clkin_wires(idx):
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wires = [
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"{tile}_CLKIN{idx}", "{tile}_FREQ_BB0", "{tile}_FREQ_BB1",
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"{tile}_FREQ_BB2", "{tile}_FREQ_BB3", "{tile}_CLK_IN{idx}_INT"
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"{tile}_CLK_IN{idx}_HCLK"
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]
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return [
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tile_name + "/" + w.format(tile=tile_type, idx=idx)
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for w in wires
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]
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params['clkin2_route'] = random.choice(
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(
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"{}_CLKIN2",
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"{}_FREQ_BB0",
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"{}_FREQ_BB1",
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"{}_FREQ_BB2",
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"{}_FREQ_BB3",
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"{}_MMCME2_CLK_IN2_INT",
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)).format(tile_type)
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params['clkin1_route'] = random.choice(get_clkin_wires(1) + hclk_wires)
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params['clkin2_route'] = random.choice(get_clkin_wires(2) + hclk_wires)
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params['clkfbin_route'] = random.choice(
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(
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"{}_CLKFBOUT2IN",
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"{}_UPPER_T_FREQ_BB0",
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"{}_UPPER_T_FREQ_BB1",
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"{}_UPPER_T_FREQ_BB2",
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"{}_UPPER_T_FREQ_BB3",
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"{}_UPPER_T_MMCME2_CLK_FB_INT",
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)).format(tile_type.replace("_UPPER_T", ""))
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"{}_FREQ_BB0",
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"{}_FREQ_BB1",
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"{}_FREQ_BB2",
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"{}_FREQ_BB3",
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"{}_CLK_IN3_INT",
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"{}_CLK_IN3_HCLK",
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)).format(tile_type)
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f.write('%s\n' % (json.dumps(params)))
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@ -191,13 +215,17 @@ module top(
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return net[:p] + '_IBUF' + net[p:]
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if params['clkin1_conn'] != "":
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net = make_ibuf_net(params['clkin1_conn'])
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wire = '{}/{}'.format(tile_name, params['clkin1_route'])
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net = params['clkin1_conn']
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if "[" in net and "]" in net:
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net = make_ibuf_net(net)
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wire = params['clkin1_route']
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routes_file.write('{} {}\n'.format(net, wire))
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if params['clkin2_conn'] != "":
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net = make_ibuf_net(params['clkin2_conn'])
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wire = '{}/{}'.format(tile_name, params['clkin2_route'])
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net = params['clkin2_conn']
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if "[" in net and "]" in net:
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net = make_ibuf_net(net)
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wire = params['clkin2_route']
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routes_file.write('{} {}\n'.format(net, wire))
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if params['clkfbin_conn'] != "" and\
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@ -239,6 +267,8 @@ module top(
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.IS_RST_INVERTED({IS_RST_INVERTED}),
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.IS_PWRDWN_INVERTED({IS_PWRDWN_INVERTED}),
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.IS_CLKINSEL_INVERTED({IS_CLKINSEL_INVERTED}),
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.IS_PSEN_INVERTED({IS_PSEN_INVERTED}),
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.IS_PSINCDEC_INVERTED({IS_PSINCDEC_INVERTED}),
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.CLKOUT0_DIVIDE_F({CLKOUT0_DIVIDE_F}),
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.CLKOUT1_DIVIDE({CLKOUT1_DIVIDE}),
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.CLKOUT2_DIVIDE({CLKOUT2_DIVIDE}),
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@ -252,6 +282,7 @@ module top(
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.CLKOUT0_DUTY_CYCLE({CLKOUT0_DUTY_CYCLE}),
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.COMPENSATION({COMPENSATION}),
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.BANDWIDTH({BANDWIDTH}),
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.SS_EN({SS_EN}),
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.CLKIN1_PERIOD(10.0),
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.CLKIN2_PERIOD(10.0)
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) pll_{site} (
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