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bitread: Rename Aux extraction methods 

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak 2020-12-01 15:24:35 +01:00
parent f00011c8fd
commit fb607b2cbc
3 changed files with 9 additions and 9 deletions
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8
lib/include/prjxray/xilinx/bitstream_reader.h
View File

@ -71,10 +71,10 @@ class BitstreamReader {
// Extract information from bitstream necessary to reconstruct RBT // Extract information from bitstream necessary to reconstruct RBT
// header and add it to the AUX data // header and add it to the AUX data
template <typename T> template <typename T>
static void ExtractHeader(T bitstream, FILE* aux_fp); static void PrintHeader(T bitstream, FILE* aux_fp);
// Extract configuration logic data and add to the AUX data // Extract configuration logic data and add to the AUX data
void ExtractFpgaConfigurationLogicData(FILE* aux_fp); void PrintFpgaConfigurationLogicData(FILE* aux_fp);
const std::vector<uint32_t>& words() { return words_; }; const std::vector<uint32_t>& words() { return words_; };
@ -93,7 +93,7 @@ class BitstreamReader {
// Extract FPGA configuration logic information // Extract FPGA configuration logic information
template <typename ArchType> template <typename ArchType>
void BitstreamReader<ArchType>::ExtractFpgaConfigurationLogicData( void BitstreamReader<ArchType>::PrintFpgaConfigurationLogicData(
FILE* aux_fp) { FILE* aux_fp) {
// Get the data before the first FDRI_WRITE command packet // Get the data before the first FDRI_WRITE command packet
const auto fpga_conf_end = std::search( const auto fpga_conf_end = std::search(
@ -118,7 +118,7 @@ void BitstreamReader<ArchType>::ExtractFpgaConfigurationLogicData(
template <typename ArchType> template <typename ArchType>
template <typename T> template <typename T>
void BitstreamReader<ArchType>::ExtractHeader(T bitstream, FILE* aux_fp) { void BitstreamReader<ArchType>::PrintHeader(T bitstream, FILE* aux_fp) {
// If this is really a Xilinx bitstream, there will be a sync // If this is really a Xilinx bitstream, there will be a sync
// word somewhere toward the beginning. // word somewhere toward the beginning.
auto sync_pos = std::search(bitstream.begin(), bitstream.end(), auto sync_pos = std::search(bitstream.begin(), bitstream.end(),

4
lib/include/prjxray/xilinx/configuration.h
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@ -68,7 +68,7 @@ class Configuration {
const typename ArchType::Part& part() const { return part_; } const typename ArchType::Part& part() const { return part_; }
const FrameMap& frames() const { return frames_; } const FrameMap& frames() const { return frames_; }
void ExtractFrameAddresses(FILE* fp); void PrintFrameAddresses(FILE* fp);
private: private:
typename ArchType::Part part_; typename ArchType::Part part_;
@ -360,7 +360,7 @@ Configuration<ArchType>::InitWithPackets(const typename ArchType::Part& part,
} }
template <typename ArchType> template <typename ArchType>
void Configuration<ArchType>::ExtractFrameAddresses(FILE* fp) { void Configuration<ArchType>::PrintFrameAddresses(FILE* fp) {
fprintf(fp, "Frame addresses in bitstream: "); fprintf(fp, "Frame addresses in bitstream: ");
for (auto frame = frames_.begin(); frame != frames_.end(); ++frame) { for (auto frame = frames_.begin(); frame != frames_.end(); ++frame) {
fprintf(fp, "%08X", (int)frame->first); fprintf(fp, "%08X", (int)frame->first);

6
tools/bitread.cc
View File

@ -129,12 +129,12 @@ struct BitReader {
return 1; return 1;
} }
// Extract and decode header information as in RBT file // Extract and decode header information as in RBT file
xilinx::BitstreamReader<ArchType>::ExtractHeader( xilinx::BitstreamReader<ArchType>::PrintHeader(
bytes_, aux_file); bytes_, aux_file);
// Extract FPGA configuration logic information // Extract FPGA configuration logic information
reader->ExtractFpgaConfigurationLogicData(aux_file); reader->PrintFpgaConfigurationLogicData(aux_file);
// Extract configuration frames' addresses // Extract configuration frames' addresses
config->ExtractFrameAddresses(aux_file); config->PrintFrameAddresses(aux_file);
fclose(aux_file); fclose(aux_file);
} }