From f71956225a6cd9703ecbfe4f9ca302fff3b5011e Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Mon, 9 Sep 2019 14:56:11 +0200 Subject: [PATCH] fuzzers: 038-cfg: Add always on bit for Zynq Signed-off-by: Tomasz Michalak --- fuzzers/038-cfg/Makefile | 5 +++++ fuzzers/038-cfg/add_constant_bits.py | 11 +++++++++++ 2 files changed, 16 insertions(+) create mode 100644 fuzzers/038-cfg/add_constant_bits.py diff --git a/fuzzers/038-cfg/Makefile b/fuzzers/038-cfg/Makefile index 4b2c308c..360ecab3 100644 --- a/fuzzers/038-cfg/Makefile +++ b/fuzzers/038-cfg/Makefile @@ -5,6 +5,11 @@ database: build/segbits_cfg.rdb ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \ --seg-fn-in build/segbits_cfg.rdb \ --seg-fn-out build/segbits_cfg.db +# Some of the bits in Zynq seem to be always set +# see https://github.com/SymbiFlow/prjxray/issues/746 +ifeq (${XRAY_DATABASE}, zynq7) + python3 add_constant_bits.py build/segbits_cfg.db +endif build/segbits_cfg.rdb: $(SPECIMENS_OK) diff --git a/fuzzers/038-cfg/add_constant_bits.py b/fuzzers/038-cfg/add_constant_bits.py new file mode 100644 index 00000000..89f68d7b --- /dev/null +++ b/fuzzers/038-cfg/add_constant_bits.py @@ -0,0 +1,11 @@ +import sys + +constant_bits = { + "CFG_CENTER_MID.ALWAYS_ON_PROP1": "26_2206", + "CFG_CENTER_MID.ALWAYS_ON_PROP2": "26_2207", + "CFG_CENTER_MID.ALWAYS_ON_PROP3": "27_2205" +} + +with open(sys.argv[1], "a") as f: + for bit_name, bit_value in constant_bits.items(): + f.write(bit_name + " " + bit_value + "\n")