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prjxray
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A lot of modifications and fixups. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-07-26 09:51:47 +02:00
parent 40d3cb5588
commit f6aecf0d88
4 changed files with 240 additions and 208 deletions
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4
fuzzers/035b-iob-iserdes/Makefile
View File

@ -1,12 +1,10 @@
N := 20 N := 50
include ../fuzzer.mk include ../fuzzer.mk
database: build/segbits_xiob33.db database: build/segbits_xiob33.db
build/segbits_xiob33.rdb: $(SPECIMENS_OK) build/segbits_xiob33.rdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt)
#python3 ~/Work/segmask.py -i build/segbits_xiob33.rdb -o build/segbits_xiob33_msk.rdb -m IN_USE
#python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt)
build/segbits_xiob33.db: build/segbits_xiob33.rdb build/segbits_xiob33.db: build/segbits_xiob33.rdb
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@

3
fuzzers/035b-iob-iserdes/bits.dbf
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@ -0,0 +1,3 @@
26_99 26_101 26_107 26_109 26_111 26_115 26_121 26_71 27_102 27_108 27_110 27_112 27_70 27_98 28_110 28_67 28_77 28_126 29_67 31_67 31_77
26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_12 27_16 27_18 27_20 27_26 27_28 27_56 28_02 28_04 28_60 29_01 29_17 29_50 29_60 30_50 30_60

172
fuzzers/035b-iob-iserdes/generate.py
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@ -15,11 +15,17 @@ with open("params.json", "r") as fp:
iface_types = [ iface_types = [
"NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR" "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"
] ]
data_rates = ["SDR", "DDR"] data_rates = ["SDR", "DDR"]
data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14]
data_widths = {
"SDR": [2, 3, 4, 5, 6, 7, 8],
"DDR": [4, 6, 8, 10, 14],
}
loc_to_tile_site_map = {}
# Output tags # Output tags
#loc_to_tile_site_map = {}
for param_list in data: for param_list in data:
for params in param_list: for params in param_list:
loc = verilog.unquote(params["SITE_LOC"]) loc = verilog.unquote(params["SITE_LOC"])
@ -28,25 +34,28 @@ for param_list in data:
get_xy = util.create_xy_fun('IOB_') get_xy = util.create_xy_fun('IOB_')
x, y = get_xy(loc) x, y = get_xy(loc)
#loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % (y % 2)
# Site not used at all # Site not used at all
if not params["IS_USED"]: if not params["IS_USED"]:
segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0)
segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 0)
segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
segmk.add_site_tag(loc, "IFF.IN_USE", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
for i in iface_types: for i in iface_types:
if i == "NETWORKING": if i == "NETWORKING":
for j in data_widths: for j in data_rates:
tag = "ISERDES.%s.%s" % (i, j) for k in data_widths[j]:
segmk.add_site_tag(loc, tag, 0) tag = "ISERDES.%s.%s.%s" % (i, j, k)
segmk.add_site_tag(loc, tag, 0)
else: else:
segmk.add_site_tag(loc, "ISERDES.%s.4" % i, 0) segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
@ -57,23 +66,30 @@ for param_list in data:
for i in range(1, 4 + 1): for i in range(1, 4 + 1):
segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
segmk.add_site_tag(loc, "ZINV_D", 0) segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1)
segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0)
segmk.add_site_tag(loc, "ZINV_D", 1)
segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "IDELMUXE3.0", 0) segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.1", 1) segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
segmk.add_site_tag(loc, "IFF.IN_USE", 0) # segmk.add_site_tag(loc, "CE1USED", 0)
# segmk.add_site_tag(loc, "IFF.SUSED", 0)
# segmk.add_site_tag(loc, "IFF.RUSED", 0)
# Site used as ISERDESE2 # Site used as ISERDESE2
elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2":
segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1)
segmk.add_site_tag(loc, "IFF.IN_USE", 0)
segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
if "SHIFTOUT_USED" in params: if "SHIFTOUT_USED" in params:
@ -94,16 +110,22 @@ for param_list in data:
data_rate = verilog.unquote(params["DATA_RATE"]) data_rate = verilog.unquote(params["DATA_RATE"])
data_width = int(params["DATA_WIDTH"]) data_width = int(params["DATA_WIDTH"])
segmk.add_site_tag(loc, "ISERDES.SDR", int(data_rate == "SDR")) #segmk.add_site_tag(loc, "ISERDES.SDR", int(data_rate == "SDR"))
segmk.add_site_tag(loc, "ISERDES.DDR", int(data_rate == "DDR")) #segmk.add_site_tag(loc, "ISERDES.DDR", int(data_rate == "DDR"))
for i in iface_types: for i in iface_types:
for j in data_widths: if i == "NETWORKING":
tag = "ISERDES.%s.%s" % (i, j) for j in data_rates:
for k in data_widths[j]:
tag = "ISERDES.%s.%s.%s" % (i, j, k)
if i == iface_type:
if j == data_rate:
if k == data_width:
segmk.add_site_tag(loc, tag, 1)
else:
if i == iface_type: if i == iface_type:
if j == data_width: segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0)
segmk.add_site_tag(loc, tag, 1)
if "NUM_CE" in params: if "NUM_CE" in params:
value = params["NUM_CE"] value = params["NUM_CE"]
@ -129,6 +151,15 @@ for param_list in data:
segmk.add_site_tag( segmk.add_site_tag(
loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
if "IS_CLKB_INVERTED" in params:
segmk.add_site_tag(
loc, "ISERDES.IS_CLKB_INVERTED",
params["IS_CLKB_INVERTED"])
if "IS_CLK_INVERTED" in params:
segmk.add_site_tag(
loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"])
if "DYN_CLKDIV_INV_EN" in params: if "DYN_CLKDIV_INV_EN" in params:
value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
segmk.add_site_tag( segmk.add_site_tag(
@ -144,69 +175,91 @@ for param_list in data:
value = verilog.unquote(params["IOBDELAY"]) value = verilog.unquote(params["IOBDELAY"])
if value == "NONE": if value == "NONE":
#segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "IDELMUXE3.0", 0) segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.1", 1) segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
if value == "IBUF": if value == "IBUF":
#segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "IDELMUXE3.0", 1) segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IDELMUXE3.1", 0) segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
if value == "IFD": if value == "IFD":
#segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
segmk.add_site_tag(loc, "IDELMUXE3.0", 0) segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.1", 1) segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
if value == "BOTH": if value == "BOTH":
#segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
segmk.add_site_tag(loc, "IDELMUXE3.0", 1) segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IDELMUXE3.1", 0) segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
if "OFB_USED" in params: if "OFB_USED" in params:
value = verilog.unquote(params["OFB_USED"]) value = verilog.unquote(params["OFB_USED"])
if value == "TRUE": segmk.add_site_tag(
segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) loc, "ISERDES.OFB_USED", int(value == "TRUE"))
# Site used as IDDR # Site used as IDDR
elif verilog.unquote(params["BEL_TYPE"]) == "IDDR": elif verilog.unquote(params["BEL_TYPE"]) == "IDDR":
segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1)
segmk.add_site_tag(loc, "IFF.IN_USE", 1) segmk.add_site_tag(loc, "IFF.IN_USE", 1)
segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
if "DDR_CLK_EDGE" in params: if "DDR_CLK_EDGE" in params:
value = verilog.unquote(params["DDR_CLK_EDGE"]) value = verilog.unquote(params["DDR_CLK_EDGE"])
segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", int(value == "OPPOSITE_EDGE")) segmk.add_site_tag(
segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", int(value == "SAME_EDGE")) loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE",
segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", int(value == "SAME_EDGE_PIPELINED")) int(value == "OPPOSITE_EDGE"))
segmk.add_site_tag(
loc, "IFF.DDR_CLK_EDGE.SAME_EDGE",
int(value == "SAME_EDGE"))
segmk.add_site_tag(
loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED",
int(value == "SAME_EDGE_PIPELINED"))
# A test
segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1)
segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0)
if "SRTYPE" in params: if "SRTYPE" in params:
value = verilog.unquote(params["SRTYPE"]) value = verilog.unquote(params["SRTYPE"])
if value == "ASYNC": if value == "ASYNC":
segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1) segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1)
segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0)
if value == "SYNC": if value == "SYNC":
segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0) segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0)
segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1)
if "IDELMUX" in params: if "IDELMUX" in params:
if params["IDELMUX"] == 1: if params["IDELMUX"] == 1:
segmk.add_site_tag(loc, "IDELMUXE3.0", 1) segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IDELMUXE3.1", 0) segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
else: else:
segmk.add_site_tag(loc, "IDELMUXE3.0", 0) segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.1", 1) segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
if "IFFDELMUX" in params: if "IFFDELMUX" in params:
if params["IFFDELMUX"] == 1: if params["IFFDELMUX"] == 1:
segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
else: else:
segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "ZINV_D", 0)
# if "CE1USED" in params:
# segmk.add_site_tag(loc, "CE1USED", params["CE1USED"])
# if "SR_MODE" in params:
# value = verilog.unquote(params["SR_MODE"])
# segmk.add_site_tag(loc, "IFF.SUSED", int(value == "SET"))
# segmk.add_site_tag(loc, "IFF.RUSED", int(value == "RST"))
segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
@ -217,13 +270,16 @@ for param_list in data:
exit(-1) exit(-1)
# Write segments and tags for later check # Write segments and tags for later check
#with open("tags.json", "w") as fp: def_tags = {t: 0 for d in segmk.site_tags.values() for t in d.keys()}
# tags = {
# loc_to_tile_site_map[l]: {k: int(v) with open("tags.json", "w") as fp:
# for k, v in d.items()} tags = {}
# for l, d in segmk.site_tags.items() for l, d in segmk.site_tags.items():
# } d1 = dict(def_tags)
# json.dump(tags, fp, sort_keys=True, indent=1) d1.update({k: int(v) for k, v in d.items()})
tags[loc_to_tile_site_map[l]] = d1
json.dump(tags, fp, sort_keys=True, indent=1)
def bitfilter(frame_idx, bit_idx): def bitfilter(frame_idx, bit_idx):

265
fuzzers/035b-iob-iserdes/top.py
View File

@ -44,75 +44,57 @@ def gen_sites():
iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0] iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
top_sites = { top_sites = {
"IOB": iob33m, "IOB": iob33m,
"ILOGIC": iob33m.replace("IOB", "ILOGIC"), "ILOGIC": iob33m.replace("IOB", "ILOGIC"),
"IDELAY": iob33m.replace("IOB", "IDELAY"), "IDELAY": iob33m.replace("IOB", "IDELAY"),
} }
bot_sites = { bot_sites = {
"IOB": iob33s, "IOB": iob33s,
"ILOGIC": iob33s.replace("IOB", "ILOGIC"), "ILOGIC": iob33s.replace("IOB", "ILOGIC"),
"IDELAY": iob33s.replace("IOB", "IDELAY"), "IDELAY": iob33s.replace("IOB", "IDELAY"),
} }
yield iob_tile_name, top_sites, bot_sites yield iob_tile_name, top_sites, bot_sites
def gen_iserdes(loc): def gen_iserdes(loc):
# Site params # Site params
params = { params = {
"SITE_LOC": "SITE_LOC": verilog.quote(loc),
verilog.quote(loc), "USE_IDELAY": random.randint(0, 1),
"IS_USED": "BEL_TYPE": verilog.quote("ISERDESE2"),
int(random.randint(0, 10) > 0), # Make it used more often "INIT_Q1": random.randint(0, 1),
"USE_IDELAY": "INIT_Q2": random.randint(0, 1),
random.randint(0, 1), "INIT_Q3": random.randint(0, 1),
"BEL_TYPE": "INIT_Q4": random.randint(0, 1),
verilog.quote("ISERDESE2"), "SRVAL_Q1": random.randint(0, 1),
"INIT_Q1": "SRVAL_Q2": random.randint(0, 1),
random.randint(0, 1), "SRVAL_Q3": random.randint(0, 1),
"INIT_Q2": "SRVAL_Q4": random.randint(0, 1),
random.randint(0, 1), "NUM_CE": random.randint(1, 2),
"INIT_Q3":
random.randint(0, 1),
"INIT_Q4":
random.randint(0, 1),
"SRVAL_Q1":
random.randint(0, 1),
"SRVAL_Q2":
random.randint(0, 1),
"SRVAL_Q3":
random.randint(0, 1),
"SRVAL_Q4":
random.randint(0, 1),
"NUM_CE":
random.randint(1, 2),
# The following one shows negative correlation (0 - not inverted) # The following one shows negative correlation (0 - not inverted)
"IS_D_INVERTED": "IS_D_INVERTED": random.randint(0, 1),
random.randint(0, 1),
# No bits were found for parameters below # No bits were found for parameters below
#"IS_OCLKB_INVERTED": random.randint(0, 1), #"IS_OCLKB_INVERTED": random.randint(0, 1),
#"IS_OCLK_INVERTED": random.randint(0, 1), #"IS_OCLK_INVERTED": random.randint(0, 1),
#"IS_CLKDIVP_INVERTED": random.randint(0, 1), #"IS_CLKDIVP_INVERTED": random.randint(0, 1),
#"IS_CLKDIV_INVERTED": random.randint(0, 1), #"IS_CLKDIV_INVERTED": random.randint(0, 1),
#"IS_CLKB_INVERTED": random.randint(0, 1), #"IS_CLKB_INVERTED":
#"IS_CLK_INVERTED": random.randint(0, 1), #random.randint(0, 1),
"DYN_CLKDIV_INV_EN": #"IS_CLK_INVERTED":
verilog.quote(random.choice(["TRUE", "FALSE"])), #random.randint(0, 1),
"DYN_CLK_INV_EN": "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
verilog.quote(random.choice(["TRUE", "FALSE"])), "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
"IOBDELAY": "IOBDELAY": verilog.quote(
verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
"OFB_USED": "OFB_USED": verilog.quote(
verilog.quote(
random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs
} }
iface_type = random.choice( iface_type = random.choice(
[ ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"])
"NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3",
"MEMORY_QDR"
])
data_rate = random.choice(["SDR", "DDR"]) data_rate = random.choice(["SDR", "DDR"])
serdes_mode = random.choice(["MASTER", "SLAVE"]) serdes_mode = random.choice(["MASTER", "SLAVE"])
@ -135,6 +117,9 @@ def gen_iserdes(loc):
if verilog.unquote(params["OFB_USED"]) == "TRUE": if verilog.unquote(params["OFB_USED"]) == "TRUE":
params["IOBDELAY"] = verilog.quote("NONE") params["IOBDELAY"] = verilog.quote("NONE")
if serdes_mode == "SLAVE":
params["IS_CLK_INVERTED"] = 0
return params return params
@ -144,8 +129,6 @@ def gen_iddr(loc):
params = { params = {
"SITE_LOC": "SITE_LOC":
verilog.quote(loc), verilog.quote(loc),
"IS_USED":
int(random.randint(0, 10) > 0), # Make it used more often
"USE_IDELAY": "USE_IDELAY":
random.randint(0, 1), random.randint(0, 1),
"BEL_TYPE": "BEL_TYPE":
@ -157,18 +140,25 @@ def gen_iddr(loc):
"SRTYPE": "SRTYPE":
verilog.quote(random.choice(["ASYNC", "SYNC"])), verilog.quote(random.choice(["ASYNC", "SYNC"])),
"DDR_CLK_EDGE": "DDR_CLK_EDGE":
verilog.quote(random.choice(["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])), verilog.quote(
random.choice(
["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])),
"CE1USED":
random.randint(0, 1),
"SR_MODE":
verilog.quote(random.choice(["NONE", "SET", "RST"])),
} }
if params["USE_IDELAY"]: if params["USE_IDELAY"]:
params["IDELMUX"] = random.randint(0, 1) params["IDELMUX"] = random.randint(0, 1)
params["IFFDELMUX"] = random.randint(0, 1) params["IFFDELMUX"] = random.randint(0, 1)
else: else:
params["IDELMUX"] = 0 params["IDELMUX"] = 0
params["IFFDELMUX"] = 0 params["IFFDELMUX"] = 0
return params return params
def run(): def run():
# Get all [LR]IOI3 tiles # Get all [LR]IOI3 tiles
@ -184,6 +174,8 @@ module top (
input wire clk1, input wire clk1,
(* CLOCK_BUFFER_TYPE = "NONE" *) (* CLOCK_BUFFER_TYPE = "NONE" *)
input wire clk2, input wire clk2,
input wire ce,
input wire rst,
input wire [{N}:0] di, input wire [{N}:0] di,
output wire [{N}:0] do output wire [{N}:0] do
); );
@ -201,100 +193,77 @@ IDELAYCTRL idelayctrl();
for i, sites in enumerate(tiles): for i, sites in enumerate(tiles):
tile_name = sites[0] tile_name = sites[0]
# # Single ISERDES # Use site
# if random.randint(0, 5) >= 1: if random.randint(0, 9) > 0: # Use more often
# Top sites # Top sites
if random.randint(0, 1): if random.randint(0, 1):
this_sites = sites[1] this_sites = sites[1]
other_sites = sites[2] other_sites = sites[2]
# Bottom sites
else:
this_sites = sites[2]
other_sites = sites[1]
# Bottom site # Generate cell
bel_types = ["IDDR", "ISERDESE2"]
bel_type = bel_types[int(
random.randint(0, 4) > 0)] # ISERDES more often
if bel_type == "ISERDESE2":
params = gen_iserdes(this_sites["ILOGIC"])
if bel_type == "IDDR":
params = gen_iddr(this_sites["ILOGIC"])
params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"])
params["IS_USED"] = 1
# Instantiate the cell
print('')
print('// This : ' + " ".join(this_sites.values()))
print('// Other: ' + " ".join(other_sites.values()))
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"])
print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"])
print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
print(
'ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));'
% (param_str, i, i, i))
params["CHAINED"] = 0
params["TILE_NAME"] = tile_name
# Params for the second site
other_params = {
"TILE_NAME": tile_name,
"SITE_LOC": verilog.quote(other_sites["ILOGIC"]),
"IDELAY_LOC": verilog.quote(other_sites["IDELAY"]),
"IS_USED": 0,
}
# Append to data list
data.append([params, other_params])
# Don't use sites
else: else:
this_sites = sites[2]
other_sites = sites[1]
# Generate cell params_list = [
bel_type = random.choice(["ISERDESE2", "IDDR"]) {
if bel_type == "ISERDESE2": "TILE_NAME": tile_name,
params = gen_iserdes(this_sites["ILOGIC"]) "SITE_LOC": verilog.quote(sites[1]["ILOGIC"]),
if bel_type == "IDDR": "IDELAY_LOC": verilog.quote(sites[1]["IDELAY"]),
params = gen_iddr(this_sites["ILOGIC"]) "IS_USED": 0,
},
{
"TILE_NAME": tile_name,
"SITE_LOC": verilog.quote(sites[2]["ILOGIC"]),
"IDELAY_LOC": verilog.quote(sites[2]["IDELAY"]),
"IS_USED": 0,
}
]
params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"]) data.append(params_list)
# Instantiate the cell
print('')
print('// This : ' + " ".join(this_sites.values()))
print('// Other: ' + " ".join(other_sites.values()))
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"])
print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"])
print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
print('ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i))
params["CHAINED"] = 0
# Params for the second site
other_params = {
"SITE_LOC": verilog.quote(other_sites["ILOGIC"]),
"IDELAY_LOC": verilog.quote(other_sites["IDELAY"]),
"IS_USED": 0,
}
# Append to data list
data.append([params, other_params])
# # Dual ISERDES chained
# else:
#
# iob_i = sites[1]
# iob_o = sites[3]
# ilogic = [sites[2], sites[4]]
#
# # Generate cells
# params_m = gen_iserdes(ilogic[0])
# params_s = gen_iserdes(ilogic[1])
#
# # Force relevant parameters
# params_m["SERDES_MODE"] = verilog.quote("MASTER")
# params_m["IS_USED"] = 1
#
# params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING")
# params_m["DATA_RATE"] = verilog.quote("DDR")
# params_m["DATA_WIDTH"] = random.choice([10, 14])
#
# params_s["SERDES_MODE"] = verilog.quote("SLAVE")
# params_s["IS_USED"] = 1
#
# params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"]
# params_s["DATA_RATE"] = params_m["DATA_RATE"]
# params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"]
#
# # Instantiate cells
# print('')
# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
# print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
# print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
#
# print('wire o_%03d_m;' % i)
# print('wire o_%03d_s;' % i)
# print('wire [1:0] sh_%03d;' % i)
# print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i))
# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items())
# print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i))
# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items())
# print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i))
#
# params_m["SHIFTOUT_USED"] = 1
#
# params_m["CHAINED"] = 1
# params_s["CHAINED"] = 1
#
# data.append([params_m, params_s])
# Store params # Store params
with open("params.json", "w") as fp: with open("params.json", "w") as fp:
@ -308,6 +277,8 @@ endmodule
module ilogic_single( module ilogic_single(
input wire clk1, input wire clk1,
input wire clk2, input wire clk2,
input wire ce,
input wire rst,
input wire I, input wire I,
output wire O, output wire O,
input wire [1:0] shiftin, input wire [1:0] shiftin,
@ -347,8 +318,10 @@ parameter IOBDELAY = "NONE";
parameter OFB_USED = "FALSE"; parameter OFB_USED = "FALSE";
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter SRTYPE = "ASYNC"; parameter SRTYPE = "ASYNC";
parameter CE1USED = 0;
parameter SR_MODE = "NONE";
wire [7:0] x; wire [8:0] x;
wire ddly; wire ddly;
(* KEEP, DONT_TOUCH *) (* KEEP, DONT_TOUCH *)
@ -422,12 +395,13 @@ generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin
.CLK(clk1), .CLK(clk1),
.CLKB(clk2), .CLKB(clk2),
.OCLK(), .OCLK(),
.OCLKB(),
.DYNCLKDIVSEL(), .DYNCLKDIVSEL(),
.CLKDIV(), .CLKDIV(),
.CLKDIVP(), .CLKDIVP(),
.RST(), .RST(),
.BITSLIP(), .BITSLIP(),
.O(), .O(x[8]),
.Q1(x[0]), .Q1(x[0]),
.Q2(x[1]), .Q2(x[1]),
.Q3(x[2]), .Q3(x[2]),
@ -456,16 +430,16 @@ end else if (IS_USED && BEL_TYPE == "IDDR") begin
iddr iddr
( (
.C(clk1), .C(clk1),
.CE(), .CE( (CE1USED) ? ce : 1'hx ),
.D( (IFFDELMUX) ? ddly : I ), .D( (IFFDELMUX) ? ddly : I ),
.S(), .S( (SR_MODE == "SET") ? rst : 1'd0 ),
.R(), .R( (SR_MODE == "RST") ? rst : 1'd0 ),
.Q1(x[0]), .Q1(x[0]),
.Q2(x[1]) .Q2(x[1])
); );
assign x[2] = (IDELMUX) ? ddly : I; assign x[8] = (IDELMUX) ? ddly : I;
assign x[7:3] = 0; assign x[7:2] = 0;
end else begin end else begin
@ -477,6 +451,7 @@ end else begin
assign x[5] = I; assign x[5] = I;
assign x[6] = I; assign x[6] = I;
assign x[7] = I; assign x[7] = I;
assign x[8] = I;
end endgenerate end endgenerate