mirror of https://github.com/openXC7/prjxray.git
Added fuzzing of IDDR along with ISERDES
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
44085d34d4
commit
40d3cb5588
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@ -1,14 +1,14 @@
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N := 50
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N := 20
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include ../fuzzer.mk
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database: build/segbits_xiob33.db
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build/segbits_xiob33_msk.rdb: $(SPECIMENS_OK)
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#${XRAY_SEGMATCH} -c -1 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt)
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build/segbits_xiob33.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt)
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#python3 ~/Work/segmask.py -i build/segbits_xiob33.rdb -o build/segbits_xiob33_msk.rdb -m IN_USE
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python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt)
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#python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt)
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build/segbits_xiob33.db: build/segbits_xiob33_msk.rdb
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build/segbits_xiob33.db: build/segbits_xiob33.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_*.txt)
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@ -30,7 +30,7 @@ for param_list in data:
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#loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2)
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# Serdes not used at all
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# Site not used at all
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if not params["IS_USED"]:
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segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0)
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@ -62,15 +62,17 @@ for param_list in data:
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segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
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segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
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# Serdes used
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else:
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segmk.add_site_tag(loc, "IFF.IN_USE", 0)
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# Site used as ISERDESE2
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elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2":
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
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@ -170,6 +172,50 @@ for param_list in data:
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if value == "TRUE":
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1)
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# Site used as IDDR
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elif verilog.unquote(params["BEL_TYPE"]) == "IDDR":
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segmk.add_site_tag(loc, "IFF.IN_USE", 1)
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if "DDR_CLK_EDGE" in params:
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value = verilog.unquote(params["DDR_CLK_EDGE"])
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segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", int(value == "OPPOSITE_EDGE"))
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segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", int(value == "SAME_EDGE"))
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segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", int(value == "SAME_EDGE_PIPELINED"))
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if "SRTYPE" in params:
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value = verilog.unquote(params["SRTYPE"])
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if value == "ASYNC":
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segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1)
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segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0)
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if value == "SYNC":
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segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0)
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segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1)
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if "IDELMUX" in params:
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if params["IDELMUX"] == 1:
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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else:
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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if "IFFDELMUX" in params:
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if params["IFFDELMUX"] == 1:
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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else:
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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# Should not happen
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else:
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print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"]))
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exit(-1)
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# Write segments and tags for later check
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#with open("tags.json", "w") as fp:
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# tags = {
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@ -14,6 +14,7 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-109}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-111}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-103}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}]
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place_design
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@ -42,10 +42,20 @@ def gen_sites():
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iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0]
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iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
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ilogic_s = iob33s.replace("IOB", "ILOGIC")
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ilogic_m = iob33m.replace("IOB", "ILOGIC")
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yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s
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top_sites = {
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"IOB": iob33m,
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"ILOGIC": iob33m.replace("IOB", "ILOGIC"),
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"IDELAY": iob33m.replace("IOB", "IDELAY"),
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}
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bot_sites = {
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"IOB": iob33s,
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"ILOGIC": iob33s.replace("IOB", "ILOGIC"),
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"IDELAY": iob33s.replace("IOB", "IDELAY"),
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}
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yield iob_tile_name, top_sites, bot_sites
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def gen_iserdes(loc):
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@ -55,6 +65,10 @@ def gen_iserdes(loc):
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verilog.quote(loc),
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"IS_USED":
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int(random.randint(0, 10) > 0), # Make it used more often
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"USE_IDELAY":
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random.randint(0, 1),
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"BEL_TYPE":
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verilog.quote("ISERDESE2"),
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"INIT_Q1":
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random.randint(0, 1),
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"INIT_Q2":
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@ -124,6 +138,37 @@ def gen_iserdes(loc):
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return params
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def gen_iddr(loc):
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# Site params
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params = {
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"SITE_LOC":
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verilog.quote(loc),
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"IS_USED":
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int(random.randint(0, 10) > 0), # Make it used more often
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"USE_IDELAY":
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random.randint(0, 1),
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"BEL_TYPE":
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verilog.quote("IDDR"),
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"INIT_Q1":
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random.randint(0, 1),
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"INIT_Q2":
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random.randint(0, 1),
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"SRTYPE":
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verilog.quote(random.choice(["ASYNC", "SYNC"])),
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"DDR_CLK_EDGE":
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verilog.quote(random.choice(["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])),
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}
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if params["USE_IDELAY"]:
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params["IDELMUX"] = random.randint(0, 1)
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params["IFFDELMUX"] = random.randint(0, 1)
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else:
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params["IDELMUX"] = 0
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params["IFFDELMUX"] = 0
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return params
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def run():
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# Get all [LR]IOI3 tiles
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@ -145,6 +190,10 @@ module top (
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wire [{N}:0] di_buf;
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wire [{N}:0] do_buf;
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// IDELAYCTRL
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(* KEEP, DONT_TOUCH *)
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IDELAYCTRL idelayctrl();
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'''.format(**{"N": len(tiles) - 1}))
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# LOCes IOBs
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@ -152,85 +201,100 @@ wire [{N}:0] do_buf;
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for i, sites in enumerate(tiles):
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tile_name = sites[0]
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# Single ISERDES
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if random.randint(0, 5) >= 1:
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# # Single ISERDES
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# if random.randint(0, 5) >= 1:
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# Bottom site
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if random.randint(0, 1):
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iob_i = sites[1]
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iob_o = sites[3]
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ilogic = sites[2]
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# Top site
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else:
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iob_i = sites[3]
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iob_o = sites[1]
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ilogic = sites[4]
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# Top sites
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if random.randint(0, 1):
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this_sites = sites[1]
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other_sites = sites[2]
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# Generate cell
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params = gen_iserdes(ilogic)
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# Instantiate the cell
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print('')
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
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print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
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print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
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print('iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i))
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params["CHAINED"] = 0
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data.append([params])
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# Dual ISERDES chained
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# Bottom site
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else:
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this_sites = sites[2]
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other_sites = sites[1]
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iob_i = sites[1]
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iob_o = sites[3]
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ilogic = [sites[2], sites[4]]
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# Generate cells
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params_m = gen_iserdes(ilogic[0])
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params_s = gen_iserdes(ilogic[1])
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# Generate cell
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bel_type = random.choice(["ISERDESE2", "IDDR"])
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if bel_type == "ISERDESE2":
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params = gen_iserdes(this_sites["ILOGIC"])
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if bel_type == "IDDR":
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params = gen_iddr(this_sites["ILOGIC"])
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# Force relevant parameters
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params_m["SERDES_MODE"] = verilog.quote("MASTER")
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params_m["IS_USED"] = 1
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params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"])
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params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING")
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params_m["DATA_RATE"] = verilog.quote("DDR")
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params_m["DATA_WIDTH"] = random.choice([10, 14])
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# Instantiate the cell
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print('')
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print('// This : ' + " ".join(this_sites.values()))
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print('// Other: ' + " ".join(other_sites.values()))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"])
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print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"])
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print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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params_s["SERDES_MODE"] = verilog.quote("SLAVE")
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params_s["IS_USED"] = 1
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
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print('ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i))
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params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"]
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params_s["DATA_RATE"] = params_m["DATA_RATE"]
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params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"]
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params["CHAINED"] = 0
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# Instantiate cells
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print('')
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
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print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
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print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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# Params for the second site
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other_params = {
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"SITE_LOC": verilog.quote(other_sites["ILOGIC"]),
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"IDELAY_LOC": verilog.quote(other_sites["IDELAY"]),
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"IS_USED": 0,
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}
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print('wire o_%03d_m;' % i)
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print('wire o_%03d_s;' % i)
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print('wire [1:0] sh_%03d;' % i)
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print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i))
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items())
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print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i))
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items())
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print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i))
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# Append to data list
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data.append([params, other_params])
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params_m["SHIFTOUT_USED"] = 1
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params_m["CHAINED"] = 1
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params_s["CHAINED"] = 1
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data.append([params_m, params_s])
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# # Dual ISERDES chained
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# else:
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#
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# iob_i = sites[1]
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# iob_o = sites[3]
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# ilogic = [sites[2], sites[4]]
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#
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# # Generate cells
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# params_m = gen_iserdes(ilogic[0])
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# params_s = gen_iserdes(ilogic[1])
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#
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# # Force relevant parameters
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# params_m["SERDES_MODE"] = verilog.quote("MASTER")
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# params_m["IS_USED"] = 1
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#
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# params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING")
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# params_m["DATA_RATE"] = verilog.quote("DDR")
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# params_m["DATA_WIDTH"] = random.choice([10, 14])
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#
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# params_s["SERDES_MODE"] = verilog.quote("SLAVE")
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# params_s["IS_USED"] = 1
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#
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# params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"]
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# params_s["DATA_RATE"] = params_m["DATA_RATE"]
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# params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"]
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#
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# # Instantiate cells
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# print('')
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# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
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# print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
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# print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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#
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# print('wire o_%03d_m;' % i)
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# print('wire o_%03d_s;' % i)
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# print('wire [1:0] sh_%03d;' % i)
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# print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i))
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# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items())
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# print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i))
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# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items())
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# print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i))
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#
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# params_m["SHIFTOUT_USED"] = 1
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#
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# params_m["CHAINED"] = 1
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# params_s["CHAINED"] = 1
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#
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||||
# data.append([params_m, params_s])
|
||||
|
||||
# Store params
|
||||
with open("params.json", "w") as fp:
|
||||
|
|
@ -241,7 +305,7 @@ wire [{N}:0] do_buf;
|
|||
endmodule
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
module iserdes_single(
|
||||
module ilogic_single(
|
||||
input wire clk1,
|
||||
input wire clk2,
|
||||
input wire I,
|
||||
|
|
@ -252,6 +316,11 @@ module iserdes_single(
|
|||
|
||||
parameter SITE_LOC = "";
|
||||
parameter IS_USED = 1;
|
||||
parameter BEL_TYPE = "ISERDESE2";
|
||||
parameter IDELAY_LOC = "";
|
||||
parameter USE_IDELAY = 0;
|
||||
parameter IDELMUX = 0;
|
||||
parameter IFFDELMUX = 0;
|
||||
parameter INTERFACE_TYPE = "NETWORKING";
|
||||
parameter DATA_RATE = "DDR";
|
||||
parameter DATA_WIDTH = 4;
|
||||
|
|
@ -276,11 +345,41 @@ parameter DYN_CLKDIV_INV_EN = "FALSE";
|
|||
parameter DYN_CLK_INV_EN = "FALSE";
|
||||
parameter IOBDELAY = "NONE";
|
||||
parameter OFB_USED = "FALSE";
|
||||
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
|
||||
parameter SRTYPE = "ASYNC";
|
||||
|
||||
wire [7:0] x;
|
||||
wire ddly;
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
generate if (IS_USED) begin
|
||||
generate if (IS_USED && USE_IDELAY) begin
|
||||
|
||||
// IDELAY
|
||||
(* LOC=IDELAY_LOC, KEEP, DONT_TOUCH *)
|
||||
IDELAYE2 idelay
|
||||
(
|
||||
.C(clk),
|
||||
.REGRST(),
|
||||
.LD(),
|
||||
.CE(),
|
||||
.INC(),
|
||||
.CINVCTRL(),
|
||||
.CNTVALUEIN(),
|
||||
.IDATAIN(I),
|
||||
.DATAIN(),
|
||||
.LDPIPEEN(),
|
||||
.DATAOUT(ddly),
|
||||
.CNTVALUEOUT()
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddly = 0;
|
||||
|
||||
end endgenerate
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin
|
||||
|
||||
// ISERDES
|
||||
(* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
|
||||
|
|
@ -343,6 +442,31 @@ generate if (IS_USED) begin
|
|||
.SHIFTOUT2(shiftout[1])
|
||||
);
|
||||
|
||||
end else if (IS_USED && BEL_TYPE == "IDDR") begin
|
||||
|
||||
// IDDR
|
||||
(* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
|
||||
IDDR #
|
||||
(
|
||||
.DDR_CLK_EDGE(DDR_CLK_EDGE),
|
||||
.INIT_Q1(INIT_Q1),
|
||||
.INIT_Q2(INIT_Q2),
|
||||
.SRTYPE(SRTYPE)
|
||||
)
|
||||
iddr
|
||||
(
|
||||
.C(clk1),
|
||||
.CE(),
|
||||
.D( (IFFDELMUX) ? ddly : I ),
|
||||
.S(),
|
||||
.R(),
|
||||
.Q1(x[0]),
|
||||
.Q2(x[1])
|
||||
);
|
||||
|
||||
assign x[2] = (IDELMUX) ? ddly : I;
|
||||
assign x[7:3] = 0;
|
||||
|
||||
end else begin
|
||||
|
||||
assign x[0] = I;
|
||||
|
|
|
|||
Loading…
Reference in New Issue