038-cfg: Add fuzzer for the CFG tile

Signed-off-by: Tomasz Michalak <[email protected]>
2026-08-22 05:57:29 +02:00 · 2019-07-13 07:10:18 +02:00
parent e8fdac9f70
commit f5ba30a81c
9 changed files with 428 additions and 0 deletions
@@ -0,0 +1,56 @@
+#!/usr/bin/env python3
+
+import json
+
+from prjxray.segmaker import Segmaker
+from prjxray import verilog
+from prjxray import segmaker
+
+
+def bitfilter(frame, word):
+    if frame < 26:
+        return False
+    return True
+
+
+def run():
+
+    segmk = Segmaker("design.bits")
+
+    print("Loading tags")
+    f = open('params.jl', 'r')
+    design = json.load(f)
+    for p in design:
+        ps = p["params"]
+        if p["site_type"] in "ICAP":
+            param = verilog.unquote(ps["ICAP_WIDTH"])
+            segmaker.add_site_group_zero(
+                segmk, p["site"], "ICAP_WIDTH_", ["X32", "X8", "X16"], "X32",
+                param)
+        elif p["site_type"] in "BSCAN":
+            param = str(ps["JTAG_CHAIN"])
+            segmaker.add_site_group_zero(
+                segmk, p["site"], "JTAG_CHAIN_", ["1", "2", "3", "4"], param,
+                param)
+        elif p["site_type"] in "CAPTURE":
+            param = verilog.unquote(ps["ONESHOT"])
+            segmk.add_site_tag(
+                p["site"], "ONESHOT", True if param in "TRUE" else False)
+        elif p["site_type"] in "STARTUP":
+            param = verilog.unquote(ps["PROG_USR"])
+            segmk.add_site_tag(
+                p["site"], "PROG_USR", True if param in "TRUE" else False)
+        elif p["site_type"] in "FRAME_ECC":
+            param = verilog.unquote(ps["FARSRC"])
+            segmaker.add_site_group_zero(
+                segmk, p["site"], "FARSRC_", ["FAR", "EFAR"], param, param)
+        elif p["site_type"] in ["USR_ACCESS", "DCIRESET"]:
+            feature = "ENABLED"
+            segmk.add_site_tag(
+                p["site"], feature, True if ps["ENABLED"] else False)
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write()
+
+
+run()