mirror of https://github.com/openXC7/prjxray.git
019_ndi1mux fuzzer for NI
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
29743571b5
commit
f56b79a5d4
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/specimen_*/
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/*.segbits
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/vivado.log
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/vivado.jou
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@ -0,0 +1,22 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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See minitest for DI notes
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#!/usr/bin/env python3
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# FIXME: getting two bits
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# 00_40 31_46
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# Can we find instance where they are not aliased?
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WA7USED = 0
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import sys, re, os
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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print("Loading tags")
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'''
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module,loc,c31,b31,a31
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my_NDI1MUX_NI_NMC31,SLICE_X12Y100,1,1,0
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my_NDI1MUX_NI_NMC31,SLICE_X12Y101,1,1,1
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my_NDI1MUX_NI_NMC31,SLICE_X12Y102,1,1,1
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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l = l.strip()
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module,loc,c31,b31,a31 = l.split(',')
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c31 = int(c31)
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b31 = int(b31)
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a31 = int(a31)
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segmk.addtag(loc, "ADI1MUX.AI", 1 ^ a31)
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segmk.addtag(loc, "BDI1MUX.BI", 1 ^ b31)
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segmk.addtag(loc, "CDI1MUX.CI", 1 ^ c31)
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segmk.compile()
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segmk.write()
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#!/bin/bash
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set -ex
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source ${XRAY_GENHEADER}
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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test -z "$(fgrep CRITICAL vivado.log)"
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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import random
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random.seed(0)
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import os
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import re
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def slice_xy():
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'''Return (X1, X2), (Y1, Y2) from XRAY_ROI, exclusive end (for xrange)'''
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# SLICE_X12Y100:SLICE_X27Y149
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# Note XRAY_ROI_GRID_* is something else
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m = re.match(r'SLICE_X(.*)Y(.*):SLICE_X(.*)Y(.*)', os.getenv('XRAY_ROI'))
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ms = [int(m.group(i + 1)) for i in range(4)]
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return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
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CLBN = 50
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SLICEX, SLICEY = slice_xy()
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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# Rearranged to sweep Y so that carry logic is easy to allocate
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# XXX: careful...if odd number of Y in ROI will break carry
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def gen_slicems():
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'''
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SLICEM at the following:
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SLICE_XxY*
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Where Y any value
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x
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Always even (ie 100, 102, 104, etc)
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In our ROI
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x = 6, 8, 10, 12, 14
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'''
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# TODO: generate this from DB
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assert((12, 28) == SLICEX)
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for slicex in (12, 14):
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for slicey in range(*SLICEY):
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# caller may reject position if needs more room
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#yield ("SLICE_X%dY%d" % (slicex, slicey), (slicex, slicey))
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,c31,b31,a31\n')
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slices = gen_slicems()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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multis = 0
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for clbi in range(CLBN):
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loc = next(slices)
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module = 'my_NDI1MUX_NI_NMC31'
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c31 = random.randint(0, 1)
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b31 = random.randint(0, 1)
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a31 = random.randint(0, 1)
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print(' %s' % module)
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print(' #(.LOC("%s"), .C31(%d), .B31(%d), .A31(%d))' % (loc, c31, b31, a31))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (clbi, 8 * clbi, 8 * clbi))
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f.write('%s,%s,%d,%d,%d\n' % (module, loc, c31, b31, a31))
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f.close()
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module my_NDI1MUX_NI_NMC31 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "SLICE_X6Y100";
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parameter C31 = 0;
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parameter B31 = 0;
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parameter A31 = 0;
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wire [3:0] q31;
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wire [3:0] lutd;
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assign lutd[3] = din[7];
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assign lutd[2] = C31 ? q31[3] : din[7];
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assign lutd[1] = B31 ? q31[2] : din[7];
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assign lutd[0] = A31 ? q31[1] : din[7];
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(* LOC=LOC, BEL="D6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[0]),
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.Q31(q31[3]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[3]));
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(* LOC=LOC, BEL="C6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[1]),
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.Q31(q31[2]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[2]));
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[2]),
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.Q31(q31[1]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[1]));
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[3]),
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.Q31(q31[0]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[0]));
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endmodule
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''')
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