mirror of https://github.com/openXC7/prjxray.git
clbram fuzzer: misc improvements
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
671b9da2eb
commit
29743571b5
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@ -1,8 +1,11 @@
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#!/usr/bin/env python3
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wip = 0
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# FIXME: getting two bits
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# 00_40 31_46
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# Can we find instance where they are not aliased?
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WA7USED = 0
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import sys, re
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import sys, re, os
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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@ -53,10 +56,8 @@ for l in f:
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WA7USED, WA8USED
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'''
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which = 'D'
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if wip:
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print(loc, 1)
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segmk.addtag(loc, "WA7USED", 1)
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segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S')
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WA7USED and segmk.addtag(loc, "WA7USED", 1)
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segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S')
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else:
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'''
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LUTD
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@ -72,19 +73,21 @@ for l in f:
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31_47: RAM mode
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'''
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for which, bel in zip('ABCD', bels):
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print(which, bel)
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segmk.addtag(loc, "%sLUT.SMALL" % which, bel in ('SRL16E', 'RAM32X1S'))
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segmk.addtag(loc, "%sLUT.SRL" % which, bel in ('SRL16E', 'SRLC32E'))
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# Only valid in D
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if which == 'D':
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segmk.addtag(loc, "%sLUT.RAM" % which, bel in ('RAM32X1S', 'RAM64X1S'))
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if wip:
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segmk.addtag(loc, "WA7USED", 0)
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#segmk.addtag(loc, "WA7USED", 1)
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print(loc, 0)
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segmk.addtag(loc, "WA8USED", 0)
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segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])
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WA7USED and segmk.addtag(loc, "WA7USED", 0)
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segmk.addtag(loc, "WA8USED", 0)
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segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])
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segmk.compile()
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def bitfilter(frame_idx, bit_idx):
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# Hack to remove aliased PIP bits
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# We should either mix up routing more or exclude previous DB entries
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assert os.getenv("XRAY_DATABASE") == "artix7"
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return (frame_idx, bit_idx) not in [(0, 27), (1, 25), (1, 26), (1, 29)]
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -42,7 +42,7 @@ endmodule
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//Activate W*MUX
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module roi(input clk, input [255:0] din, output [255:0] dout);
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module roi_sdffd(input clk, input [255:0] din, output [255:0] dout);
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/*
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seg SEG_CLBLM_L_X10Y100
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bit 00_40
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@ -86,8 +86,10 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
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bit 31_16
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bit 31_47
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*/
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/*
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my_RAM64X1S_2 #(.LOC("SLICE_X12Y104"))
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c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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*/
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endmodule
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//It created a LUT instead of aggregating using WA7MUX
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@ -520,47 +522,114 @@ module roi_asdsdaf(input clk, input [255:0] din, output [255:0] dout);
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endmodule
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//One of each
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module roi_asdfsadf(input clk, input [255:0] din, output [255:0] dout);
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module roi(input clk, input [255:0] din, output [255:0] dout);
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y100
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM64X1D2 #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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//1LUT
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/*
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seg SEG_CLBLM_L_X10Y101
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bit 00_00
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*/
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my_SRLC32E #(.LOC("SLICE_X12Y101"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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//1LUT
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/*
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No unknown bits
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*/
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my_SRL16E #(.LOC("SLICE_X12Y102"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y103
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bit 00_00
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bit 00_20
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bit 01_43
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM64M #(.LOC("SLICE_X12Y103"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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//1LUT
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/*
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No unknown bits
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*/
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my_RAM64X1S #(.LOC("SLICE_X12Y104"))
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c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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//1LUT
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/*
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No unknown bits
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*/
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my_RAM64X1S_1 #(.LOC("SLICE_X12Y105"))
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c5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y106
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bit 01_43
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bit 31_46
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*/
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my_RAM64X2S #(.LOC("SLICE_X12Y106"))
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c6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y107
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bit 31_46
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*/
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my_RAM64X1D #(.LOC("SLICE_X12Y107"))
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c7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y108
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bit 00_40
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM128X1D #(.LOC("SLICE_X12Y108"))
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c8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y109
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bit 00_00
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bit 00_20
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bit 01_43
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM32M #(.LOC("SLICE_X12Y109"))
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c9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y110
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bit 31_46
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*/
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my_RAM32X1D #(.LOC("SLICE_X12Y110"))
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c10(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
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//1LUT
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/*
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No bits
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*/
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my_RAM32X1S #(.LOC("SLICE_X12Y111"))
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c11(.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 88 +: 8]));
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//1LUT
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/*
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No bits
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*/
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my_RAM32X1S_1 #(.LOC("SLICE_X12Y112"))
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c12(.clk(clk), .din(din[ 96 +: 8]), .dout(dout[ 96 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y113
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bit 31_46
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*/
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my_RAM32X2S #(.LOC("SLICE_X12Y113"))
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c13(.clk(clk), .din(din[ 104 +: 8]), .dout(dout[ 104 +: 8]));
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endmodule
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