luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ffconfig readme: cleanup 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2019-01-11 16:06:49 +01:00
parent 09971f8bd4
commit f4f2a79cf9
1 changed files with 89 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

140
fuzzers/011-clb-ffconfig/README.md
View File

@ -1,11 +1,11 @@
# FFConfig Fuzzer # FFConfig Fuzzer
Tags for CLB tiles use a dot-separated hierarchy for their tag names. For example the tag `CLBLL_L.SLICEL_X0.ALUT.INIT[00]` documents the bit position of the LSB LUT init bit for the ALUT for the slice with even X coordinate within a `CLBLL_L` tile. (There are 4 LUTs in a slice: ALUT, BLUT, CLUT, and DLUT. And there are two slices in a CLB tile: One with an even X coordinate using the `SLICEL_X0` namespace for tags, and one with an odd X coordinate using the `SLICEL_X1` namespace for tags.) Note Vivado GUI is misleading in some cases where it shows configuration per FF, but its actually per SLICE
Also note mapping between FF/latch library elements and CLB FF's: ## Primitive pin map
| Element | CE | CK | D | SR | Q | | Element | CE | CK | D | SR | Q |
| ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | |----------|----|----|---|-----|---|
| FDRE | CE | C | D | R | Q | | FDRE | CE | C | D | R | Q |
| FDPE | CE | C | D | PRE | Q | | FDPE | CE | C | D | PRE | Q |
| FDSE | CE | C | D | S | Q | | FDSE | CE | C | D | S | Q |
@ -13,82 +13,108 @@ Also note mapping between FF/latch library elements and CLB FF's:
| LDPE | GE | G | D | PRE | Q | | LDPE | GE | G | D | PRE | Q |
| LDCE | GE | G | D | CLR | Q | | LDCE | GE | G | D | CLR | Q |
And required configuration (as noted below):
| Element | FFSYNC | LATCH | ZRST | ## Primitive bit map
| ------------- | ------------- | ------------- | ------------- |
| FDPE | | | | | Prim | FFSYNC | LATCH | ZRST |
| FDSE | 1 | | | |------|--------|-------|------|
| FDRE | 1 | | 1 | |FDPE | | | |
| FDCE | | | 1 | |FDSE | X | | |
| LDCE | | 1 | 1 | |FDRE | X | | X |
| LDPE | | 1 | | |FDCE | | | X |
|LDCE | | X | X |
|LDPE | | X | |
## CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]*FF.ZINI ### FFSYNC
Sets GSR FF or latch value Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
FF Scope: entire site (not individual FFs)
* 0: reset / initialize to 1
* 1: reset / initialize to 0
Latch | FFSYNC | Reset | Applicable prims |
* 0: reset / initialize to 0 |--------|--------------|---------------------------|
* 1: reset / initialize to 1 |0 | Synchronous | FDPE, FDCE, LDCE, LDPE |
|1 | Asynchronous | FDSE, FDRE |
## CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]*FF.ZRST
Set when reset signal should set storage element to 0. Specifically: ### LATCH
* 0: FDRE, FDCE, and LDCE primitives Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
* 1: FDPE, FDSE, and LDPE primitives
## CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]LUT.INIT
TBD
## CLBL[LM]_[LR].SLICE[LM]_X[01].FFSYNC
Unlike most bits, shared between all CLB FFs
* 0: synchronous reset, specifically FDPE, FDCE, LDCE, and LDPE primitives
* 1: asynchronous reset, specifically FDSE and FDRE primitives
## CLBL[LM]_[LR].SLICE[LM]_X[01].LATCH
Controls latch vs FF behavior for the CLB Controls latch vs FF behavior for the CLB
* 0: all storage elements in the CLB are FF's | LATCH | Description | Primitives |
* 1: LUT6 storage elements are latches (LDCE or LDPE). LUT5 storage elements cannot be used |-------|-------------|------------|
|0 | All storage elements in the CLB are FF's | FDPE, FDSE, FDRE, FDCE |
|1 | LUT6 storage elements are latches (LDCE or LDPE). LUT5 storage elements cannot be used | LDCE, LDPE |
## CLBL[LM]_[LR].SLICE[LM]_X[01].CEUSEDMUX
### [ABCD]*FF.ZRST
Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
Configured stored value when reset is asserted
| Prim |ZRST|On reset|
|-----------------------|----|----- |
|FDRE, FDCE, and LDCE | 0 | 1 |
|FDRE, FDCE, and LDCE | 1 | 0 |
|FDPE, FDSE, and LDPE | 0 | 0 |
|FDPE, FDSE, and LDPE | 1 | 1 |
## [ABCD]*FF.ZINI
Sets GSR FF or latch value
Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
| LATCH | ZINI | Set to |
|-------|------|--------|
| FF | 0 | 1 |
| FF | 1 | 0 |
| LATCH | 0 | 0 |
| LATCH | 1 | 1 |
## CEUSEDMUX
Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
Configure ability to drive clock enable (CE) or always enable clock Configure ability to drive clock enable (CE) or always enable clock
* 0: always on (CE=1)
* 1: controlled (CE=mywire)
## CLBL[LM]_[LR].SLICE[LM]_X[01].SRUSEDMUX | CEUSEDMUX | Description |
|-----------|-------------------------|
| 0 | always on (CE=1) |
| 1 | controlled (CE=mywire) |
## SRUSEDMUX
Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
Configure ability to reset FF after GSR Configure ability to reset FF after GSR
* 0: never reset (R=0)
* 1: controlled (R=mywire) | SRUSEDMUX | Description |
|-----------|-----------------------|
| 0 | never reset (R=0) |
| 1 | controlled (R=mywire) |
TODO: how used when SR? TODO: how used when SR?
## CLBL[LM]_[LR].SLICE[LM]_X[01].CLKINV ## CLKINV
Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
Scope: entire site (not individual FFs)
Whether to invert the clock going into a slice. Whether to invert the clock going into a slice.
FF: | LATCH | CLKINV | Description |
* 0: normal clock |-------|--------|----------------|
* 1: invert clock | FF | 0 | normal clock |
| FF | 1 | invert clock |
Latch: | LATCH | 0 | invert clock |
* 0: invert clock | LATCH | 1 | normal clock |
* 1: normal clock
That is, for example, FDSE_1 will have the bit set, but LDCE_1 will have the bit clear.
Note: clock cannot be inverted at individual FF's