mirror of https://github.com/openXC7/prjxray.git
Added changing of clock inverters / updated bits.dbf
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
ebf88a8430
commit
e68b3083d4
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@ -1,6 +1,12 @@
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26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE
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26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE
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26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE
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26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE
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IOI3.ILOGIC_Y0.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IDELMUXE3.P1
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IOI3.ILOGIC_Y0.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IFFDELMUXE3.P1
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IOI3.ILOGIC_Y1.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IDELMUXE3.P1
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IOI3.ILOGIC_Y1.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IFFDELMUXE3.P1
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26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE
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26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE
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26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE
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26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE
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26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112
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26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26
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@ -34,7 +34,7 @@ def run():
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loc = verilog.unquote(params["SITE_LOC"])
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get_xy = util.create_xy_fun('IOB_')
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x, y = get_xy(loc)
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x, y = get_xy(loc.replace("ILOGIC", "IOB"))
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loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % (
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y % 2)
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@ -60,8 +60,8 @@ def run():
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else:
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segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
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for i in range(1, 4 + 1):
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segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
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@ -112,6 +112,7 @@ def run():
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for j in data_rates:
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for k in data_widths[j]:
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tag = "ISERDES.%s.%s.%s" % (i, j, k)
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val = 0
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if i == iface_type:
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if j == data_rate:
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@ -124,11 +125,11 @@ def run():
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if "NUM_CE" in params:
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value = params["NUM_CE"]
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if value == 1:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
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if value == 2:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 1)
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for i in range(1, 4 + 1):
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if ("INIT_Q%d" % i) in params:
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@ -142,18 +143,15 @@ def run():
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loc, "IFF.ZSRVAL_Q%d" % i,
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not params["SRVAL_Q%d" % i])
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if "IS_D_INVERTED" in params:
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segmk.add_site_tag(
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loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
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# if "IS_CLKB_INVERTED" in params:
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# segmk.add_site_tag(
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# loc, "ISERDES.IS_CLKB_INVERTED",
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# params["IS_CLKB_INVERTED"])
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# if "IS_CLK_INVERTED" in params:
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# segmk.add_site_tag(
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# loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"])
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for inv in ["CLK", "CLKB", "OCLK", "OCLKB", "CLKDIV",
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"CLKDIVP"]:
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if "IS_{}_INVERTED".format(inv) in params:
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segmk.add_site_tag(
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loc, "ISERDES.INV_{}".format(inv),
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params["IS_{}_INVERTED".format(inv)])
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segmk.add_site_tag(
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loc, "ISERDES.ZINV_{}".format(inv),
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not params["IS_{}_INVERTED".format(inv)])
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if "DYN_CLKDIV_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
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@ -238,8 +236,17 @@ def run():
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segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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for inv in ["C", "D"]:
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if "IS_{}_INVERTED".format(inv) in params:
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segmk.add_site_tag(
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loc, "INV_{}".format(inv),
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params["IS_{}_INVERTED".format(inv)])
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segmk.add_site_tag(
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loc, "ZINV_{}".format(inv),
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not params["IS_{}_INVERTED".format(inv)])
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
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# Should not happen
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else:
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@ -117,9 +117,6 @@ def gen_iserdes(loc):
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if verilog.unquote(params["OFB_USED"]) == "TRUE":
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params["IOBDELAY"] = verilog.quote("NONE")
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if serdes_mode == "SLAVE":
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params["IS_CLK_INVERTED"] = 0
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return params
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@ -147,6 +144,10 @@ def gen_iddr(loc):
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random.randint(0, 1),
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"SR_MODE":
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verilog.quote(random.choice(["NONE", "SET", "RST"])),
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"IS_C_INVERTED":
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random.randint(0, 1),
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"IS_D_INVERTED":
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random.randint(0, 1),
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}
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if params["USE_IDELAY"]:
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@ -208,7 +209,7 @@ IDELAYCTRL idelayctrl();
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# Generate cell
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bel_types = ["IDDR", "ISERDESE2"]
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bel_type = bel_types[int(
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random.randint(0, 19) > 0)] # ISERDES more often
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random.randint(0, 2) > 0)] # ISERDES more often
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if bel_type == "ISERDESE2":
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params = gen_iserdes(this_sites["ILOGIC"])
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if bel_type == "IDDR":
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@ -322,6 +323,7 @@ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
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parameter SRTYPE = "ASYNC";
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parameter CE1USED = 0;
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parameter SR_MODE = "NONE";
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parameter IS_C_INVERTED = 0;
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wire [8:0] x;
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wire ddly;
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@ -424,6 +426,8 @@ end else if (IS_USED && BEL_TYPE == "IDDR") begin
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(* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
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IDDR #
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(
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.DDR_CLK_EDGE(DDR_CLK_EDGE),
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.INIT_Q1(INIT_Q1),
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.INIT_Q2(INIT_Q2),
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