From e68b3083d4431274422b14b998463d03a51f94e0 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 25 Nov 2019 16:13:49 +0100 Subject: [PATCH] Added changing of clock inverters / updated bits.dbf Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/bits.dbf | 14 +++++--- fuzzers/035b-iob-iserdes/generate.py | 49 ++++++++++++++++------------ fuzzers/035b-iob-iserdes/top.py | 12 ++++--- 3 files changed, 46 insertions(+), 29 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 7a400432..63a90990 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -1,6 +1,12 @@ -26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE -26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE -26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE -26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE +IOI3.ILOGIC_Y0.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IDELMUXE3.P1 +IOI3.ILOGIC_Y0.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IFFDELMUXE3.P1 +IOI3.ILOGIC_Y1.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IDELMUXE3.P1 +IOI3.ILOGIC_Y1.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IFFDELMUXE3.P1 + +26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE +26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE +26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE +26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE + 26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 5e407f38..c2ac5e39 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -34,7 +34,7 @@ def run(): loc = verilog.unquote(params["SITE_LOC"]) get_xy = util.create_xy_fun('IOB_') - x, y = get_xy(loc) + x, y = get_xy(loc.replace("ILOGIC", "IOB")) loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % ( y % 2) @@ -60,8 +60,8 @@ def run(): else: segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) @@ -112,6 +112,7 @@ def run(): for j in data_rates: for k in data_widths[j]: tag = "ISERDES.%s.%s.%s" % (i, j, k) + val = 0 if i == iface_type: if j == data_rate: @@ -124,11 +125,11 @@ def run(): if "NUM_CE" in params: value = params["NUM_CE"] if value == 1: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) if value == 2: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 1) for i in range(1, 4 + 1): if ("INIT_Q%d" % i) in params: @@ -142,18 +143,15 @@ def run(): loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) - if "IS_D_INVERTED" in params: - segmk.add_site_tag( - loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) - - # if "IS_CLKB_INVERTED" in params: - # segmk.add_site_tag( - # loc, "ISERDES.IS_CLKB_INVERTED", - # params["IS_CLKB_INVERTED"]) - - # if "IS_CLK_INVERTED" in params: - # segmk.add_site_tag( - # loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"]) + for inv in ["CLK", "CLKB", "OCLK", "OCLKB", "CLKDIV", + "CLKDIVP"]: + if "IS_{}_INVERTED".format(inv) in params: + segmk.add_site_tag( + loc, "ISERDES.INV_{}".format(inv), + params["IS_{}_INVERTED".format(inv)]) + segmk.add_site_tag( + loc, "ISERDES.ZINV_{}".format(inv), + not params["IS_{}_INVERTED".format(inv)]) if "DYN_CLKDIV_INV_EN" in params: value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) @@ -238,8 +236,17 @@ def run(): segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + for inv in ["C", "D"]: + if "IS_{}_INVERTED".format(inv) in params: + segmk.add_site_tag( + loc, "INV_{}".format(inv), + params["IS_{}_INVERTED".format(inv)]) + segmk.add_site_tag( + loc, "ZINV_{}".format(inv), + not params["IS_{}_INVERTED".format(inv)]) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) # Should not happen else: diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index ffe962ef..b1ff01ea 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -117,9 +117,6 @@ def gen_iserdes(loc): if verilog.unquote(params["OFB_USED"]) == "TRUE": params["IOBDELAY"] = verilog.quote("NONE") - if serdes_mode == "SLAVE": - params["IS_CLK_INVERTED"] = 0 - return params @@ -147,6 +144,10 @@ def gen_iddr(loc): random.randint(0, 1), "SR_MODE": verilog.quote(random.choice(["NONE", "SET", "RST"])), + "IS_C_INVERTED": + random.randint(0, 1), + "IS_D_INVERTED": + random.randint(0, 1), } if params["USE_IDELAY"]: @@ -208,7 +209,7 @@ IDELAYCTRL idelayctrl(); # Generate cell bel_types = ["IDDR", "ISERDESE2"] bel_type = bel_types[int( - random.randint(0, 19) > 0)] # ISERDES more often + random.randint(0, 2) > 0)] # ISERDES more often if bel_type == "ISERDESE2": params = gen_iserdes(this_sites["ILOGIC"]) if bel_type == "IDDR": @@ -322,6 +323,7 @@ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter SRTYPE = "ASYNC"; parameter CE1USED = 0; parameter SR_MODE = "NONE"; +parameter IS_C_INVERTED = 0; wire [8:0] x; wire ddly; @@ -424,6 +426,8 @@ end else if (IS_USED && BEL_TYPE == "IDDR") begin (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) IDDR # ( + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), .DDR_CLK_EDGE(DDR_CLK_EDGE), .INIT_Q1(INIT_Q1), .INIT_Q2(INIT_Q2),