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fuzzers: replace inline verilog with top_harnesS() 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-10-23 14:27:08 -07:00
parent afdb7a96d8
commit e3b300765e
9 changed files with 18 additions and 270 deletions
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32
fuzzers/011-ffconfig/top.py
View File

@ -1,6 +1,7 @@
import random
random.seed(0)
from prjxray import util
from prjxray import verilog
from prims import *
@ -22,36 +23,7 @@ def gen_slices():
DIN_N = CLBN * 4
DOUT_N = CLBN * 1
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
slices = gen_slices()
print(

32
fuzzers/012-clbn5ffmux/top.py
View File

@ -1,6 +1,7 @@
import random
random.seed(0)
from prjxray import util
from prjxray import verilog
CLBN = 40
print('//Requested CLBs: %s' % str(CLBN))
@ -15,36 +16,7 @@ def gen_slices():
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,n,def_a\n')

32
fuzzers/013-clbncy0/top.py
View File

@ -1,6 +1,7 @@
import random
random.seed(0)
from prjxray import util
from prjxray import verilog
CLBN = 400
print('//Requested CLBs: %s' % str(CLBN))
@ -17,36 +18,7 @@ DOUT_N = CLBN * 8
lut_bels = ['A6LUT', 'B6LUT', 'C6LUT', 'D6LUT']
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,bel,n\n')

32
fuzzers/014-ffsrcemux/top.py
View File

@ -3,6 +3,7 @@ random.seed(0)
import os
import re
from prjxray import util
from prjxray import verilog
CLBN = 600
print('//Requested CLBs: %s' % str(CLBN))
@ -28,36 +29,7 @@ ff_bels = (
'D5FF',
)
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('name,loc,ce,r\n')

32
fuzzers/015-clbnffmux/top.py
View File

@ -1,6 +1,7 @@
import random
random.seed(0)
from prjxray import util
from prjxray import verilog
CLBN = 400
print('//Requested CLBs: %s' % str(CLBN))
@ -17,36 +18,7 @@ def gen_slices():
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,n\n')

32
fuzzers/016-clbnoutmux/top.py
View File

@ -1,6 +1,7 @@
import random
random.seed(0)
from prjxray import util
from prjxray import verilog
CLBN = 400
print('//Requested CLBs: %s' % str(CLBN))
@ -15,36 +16,7 @@ def gen_slices():
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,n\n')

32
fuzzers/017-clbprecyinit/top.py
View File

@ -2,6 +2,7 @@ import random
random.seed(0)
import os
import re
from prjxray import verilog
def slice_xy():
@ -37,36 +38,7 @@ def gen_slices():
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,loc2\n')

32
fuzzers/018-clbram/top.py
View File

@ -18,6 +18,7 @@ Note: LUT6 was added to try to simplify reduction, although it might not be need
import random
random.seed(0)
from prjxray import util
from prjxray import verilog
CLBN = 50
print('//Requested CLBs: %s' % str(CLBN))
@ -32,36 +33,7 @@ def gen_slicems():
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,bela,belb,belc,beld\n')

32
fuzzers/019-ndi1mux/top.py
View File

@ -1,6 +1,7 @@
import random
random.seed(0)
from prjxray import util
from prjxray import verilog
CLBN = 50
print('//Requested CLBs: %s' % str(CLBN))
@ -15,36 +16,7 @@ def gen_slicems():
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = %d;
localparam integer DOUT_N = %d;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
''' % (DIN_N, DOUT_N))
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,c31,b31,a31\n')