From e3b300765e0338b7fe6d5da692f2d184f80e6d50 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Tue, 23 Oct 2018 14:27:08 -0700 Subject: [PATCH] fuzzers: replace inline verilog with top_harnesS() Signed-off-by: John McMaster --- fuzzers/011-ffconfig/top.py | 32 ++------------------------------ fuzzers/012-clbn5ffmux/top.py | 32 ++------------------------------ fuzzers/013-clbncy0/top.py | 32 ++------------------------------ fuzzers/014-ffsrcemux/top.py | 32 ++------------------------------ fuzzers/015-clbnffmux/top.py | 32 ++------------------------------ fuzzers/016-clbnoutmux/top.py | 32 ++------------------------------ fuzzers/017-clbprecyinit/top.py | 32 ++------------------------------ fuzzers/018-clbram/top.py | 32 ++------------------------------ fuzzers/019-ndi1mux/top.py | 32 ++------------------------------ 9 files changed, 18 insertions(+), 270 deletions(-) diff --git a/fuzzers/011-ffconfig/top.py b/fuzzers/011-ffconfig/top.py index e7bc479f..87106984 100644 --- a/fuzzers/011-ffconfig/top.py +++ b/fuzzers/011-ffconfig/top.py @@ -1,6 +1,7 @@ import random random.seed(0) from prjxray import util +from prjxray import verilog from prims import * @@ -22,36 +23,7 @@ def gen_slices(): DIN_N = CLBN * 4 DOUT_N = CLBN * 1 -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) slices = gen_slices() print( diff --git a/fuzzers/012-clbn5ffmux/top.py b/fuzzers/012-clbn5ffmux/top.py index e7d25219..8d2ec5d9 100644 --- a/fuzzers/012-clbn5ffmux/top.py +++ b/fuzzers/012-clbn5ffmux/top.py @@ -1,6 +1,7 @@ import random random.seed(0) from prjxray import util +from prjxray import verilog CLBN = 40 print('//Requested CLBs: %s' % str(CLBN)) @@ -15,36 +16,7 @@ def gen_slices(): DIN_N = CLBN * 8 DOUT_N = CLBN * 8 -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,n,def_a\n') diff --git a/fuzzers/013-clbncy0/top.py b/fuzzers/013-clbncy0/top.py index 4069a8f4..81bf0f89 100644 --- a/fuzzers/013-clbncy0/top.py +++ b/fuzzers/013-clbncy0/top.py @@ -1,6 +1,7 @@ import random random.seed(0) from prjxray import util +from prjxray import verilog CLBN = 400 print('//Requested CLBs: %s' % str(CLBN)) @@ -17,36 +18,7 @@ DOUT_N = CLBN * 8 lut_bels = ['A6LUT', 'B6LUT', 'C6LUT', 'D6LUT'] -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,bel,n\n') diff --git a/fuzzers/014-ffsrcemux/top.py b/fuzzers/014-ffsrcemux/top.py index dea5afb8..f56c3029 100644 --- a/fuzzers/014-ffsrcemux/top.py +++ b/fuzzers/014-ffsrcemux/top.py @@ -3,6 +3,7 @@ random.seed(0) import os import re from prjxray import util +from prjxray import verilog CLBN = 600 print('//Requested CLBs: %s' % str(CLBN)) @@ -28,36 +29,7 @@ ff_bels = ( 'D5FF', ) -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('name,loc,ce,r\n') diff --git a/fuzzers/015-clbnffmux/top.py b/fuzzers/015-clbnffmux/top.py index 352f1fd8..d233b89f 100644 --- a/fuzzers/015-clbnffmux/top.py +++ b/fuzzers/015-clbnffmux/top.py @@ -1,6 +1,7 @@ import random random.seed(0) from prjxray import util +from prjxray import verilog CLBN = 400 print('//Requested CLBs: %s' % str(CLBN)) @@ -17,36 +18,7 @@ def gen_slices(): DIN_N = CLBN * 8 DOUT_N = CLBN * 8 -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,n\n') diff --git a/fuzzers/016-clbnoutmux/top.py b/fuzzers/016-clbnoutmux/top.py index 068a38eb..4cc660c0 100644 --- a/fuzzers/016-clbnoutmux/top.py +++ b/fuzzers/016-clbnoutmux/top.py @@ -1,6 +1,7 @@ import random random.seed(0) from prjxray import util +from prjxray import verilog CLBN = 400 print('//Requested CLBs: %s' % str(CLBN)) @@ -15,36 +16,7 @@ def gen_slices(): DIN_N = CLBN * 8 DOUT_N = CLBN * 8 -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,n\n') diff --git a/fuzzers/017-clbprecyinit/top.py b/fuzzers/017-clbprecyinit/top.py index 908b65a0..47718a6c 100644 --- a/fuzzers/017-clbprecyinit/top.py +++ b/fuzzers/017-clbprecyinit/top.py @@ -2,6 +2,7 @@ import random random.seed(0) import os import re +from prjxray import verilog def slice_xy(): @@ -37,36 +38,7 @@ def gen_slices(): DIN_N = CLBN * 8 DOUT_N = CLBN * 8 -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,loc2\n') diff --git a/fuzzers/018-clbram/top.py b/fuzzers/018-clbram/top.py index 97247283..b612a2c0 100644 --- a/fuzzers/018-clbram/top.py +++ b/fuzzers/018-clbram/top.py @@ -18,6 +18,7 @@ Note: LUT6 was added to try to simplify reduction, although it might not be need import random random.seed(0) from prjxray import util +from prjxray import verilog CLBN = 50 print('//Requested CLBs: %s' % str(CLBN)) @@ -32,36 +33,7 @@ def gen_slicems(): DIN_N = CLBN * 8 DOUT_N = CLBN * 8 -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,bela,belb,belc,beld\n') diff --git a/fuzzers/019-ndi1mux/top.py b/fuzzers/019-ndi1mux/top.py index 10c6a75a..5966a563 100644 --- a/fuzzers/019-ndi1mux/top.py +++ b/fuzzers/019-ndi1mux/top.py @@ -1,6 +1,7 @@ import random random.seed(0) from prjxray import util +from prjxray import verilog CLBN = 50 print('//Requested CLBs: %s' % str(CLBN)) @@ -15,36 +16,7 @@ def gen_slicems(): DIN_N = CLBN * 8 DOUT_N = CLBN * 8 -print( - ''' -module top(input clk, stb, di, output do); - localparam integer DIN_N = %d; - localparam integer DOUT_N = %d; - - reg [DIN_N-1:0] din; - wire [DOUT_N-1:0] dout; - - reg [DIN_N-1:0] din_shr; - reg [DOUT_N-1:0] dout_shr; - - always @(posedge clk) begin - din_shr <= {din_shr, di}; - dout_shr <= {dout_shr, din_shr[DIN_N-1]}; - if (stb) begin - din <= din_shr; - dout_shr <= dout; - end - end - - assign do = dout_shr[DOUT_N-1]; - - roi roi ( - .clk(clk), - .din(din), - .dout(dout) - ); -endmodule -''' % (DIN_N, DOUT_N)) +verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,c31,b31,a31\n')