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Merge pull request #441 from emka/clkout_divide

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Add all CLKOUT1_DIVIDE bits
This commit is contained in:
John Mcmaster
2019-01-06 12:29:41 +01:00
committed by GitHub
parent 4b8f3b0eb8 540999acdf
commit dd26facddf
3 changed files with 62 additions and 27 deletions
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fuzzers/031-mmcm/Makefile
+1 -1
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@@ -1,6 +1,6 @@
# read/write width is relatively slow to resolve # read/write width is relatively slow to resolve
# Even slower with multi bit masks... # Even slower with multi bit masks...
N := 8 N := 14
include ../fuzzer.mk include ../fuzzer.mk
SEGDATAS=$(addsuffix /segdata_cmt_top_r_lower_b.txt,$(SPECIMENS)) SEGDATAS=$(addsuffix /segdata_cmt_top_r_lower_b.txt,$(SPECIMENS))
fuzzers/031-mmcm/generate.py
+32 -14
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@@ -7,22 +7,40 @@ from prjxray import verilog
def clkout_tags(segmk, ps, site): def clkout_tags(segmk, ps, site):
""" Notes: """
First bit is only active for value 1, for 1-128 in total 14 bits are toggling. Special bit for value 1 (bypass), all bits off for value 128.
The relation is not clear yet, multiplication of the value by 2 does not fully correlate. Two 7 bit counters, sharing LSB (one counter is value+1, inverting the LSB).
""" """
for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]: for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]:
# 1-128 => 0-127 for actual 7 bit value value = int(ps[param])
paramadj = 2 * int(ps[param])
bitstr = [int(x) for x in "{0:08b}".format(paramadj)[::-1]] # bypass bit
# FIXME: only bits 0 and 1 resolving segmk.add_site_tag(site, '%s_NODIV' % param, value == 1)
for i in range(8):
# for i in range(2): bitstr = [int(x) for x in "{0:08b}".format(value)[::-1]]
#if i in [0, 3, 5]: bitstr2 = [int(x) for x in "{0:08b}".format(value + 1)[::-1]]
# mybit = 1 ^ bitstr[i] for i in range(7):
#else:
mybit = bitstr[i] mybit = bitstr[i]
segmk.add_site_tag(site, '%s[%u]' % (param, i), mybit) mybit2 = bitstr2[i]
if i == 0:
# shared (inverted) LSB
mybit2 = 1 ^ bitstr2[i]
assert mybit == mybit2, "{} value {} has invalid bit0 at".format(
param, value)
# special cases
if value == 1:
if i == 0:
mybit = 0
mybit2 = 0
elif i == 1:
mybit = 1
elif value == 128:
mybit = 0
mybit2 = 0
segmk.add_site_tag(site, '%s_CNT0_[%u]' % (param, i), mybit)
segmk.add_site_tag(site, '%s_CNT1_[%u]' % (param, i), mybit2)
def misc_tags(segmk, ps, site): def misc_tags(segmk, ps, site):
@@ -54,7 +72,7 @@ def run():
assert j['module'] == 'my_MMCME2_ADV' assert j['module'] == 'my_MMCME2_ADV'
site = verilog.unquote(ps['LOC']) site = verilog.unquote(ps['LOC'])
#clkout_tags(segmk, ps, site) clkout_tags(segmk, ps, site)
misc_tags(segmk, ps, site) misc_tags(segmk, ps, site)
segmk.compile() segmk.compile()
fuzzers/031-mmcm/top.py
+29 -12
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@@ -6,6 +6,7 @@ from prjxray import verilog
from prjxray.verilog import vrandbit, vrandbits from prjxray.verilog import vrandbit, vrandbits
import sys import sys
import json import json
import numpy as np
def gen_sites(): def gen_sites():
@@ -36,18 +37,34 @@ for loci, site in enumerate(sites):
} }
params = { params = {
"CLKOUT1_DIVIDE": random.randint(1, 128), "CLKOUT1_DIVIDE":
"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]), int(
"CLKOUT4_CASCADE": random.choice(["\"TRUE\"", "\"FALSE\""]), np.random.choice(
"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]), [1, 63, 127, 128, random.randint(2, 127)],
"CLKFBOUT_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), p=[0.2, 0.1, 0.1, 0.1,
"CLKOUT0_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), 0.5])), # make sure that special values are present
"CLKOUT1_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), "STARTUP_WAIT":
"CLKOUT2_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT3_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), "CLKOUT4_CASCADE":
"CLKOUT4_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT5_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), "STARTUP_WAIT":
"CLKOUT6_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]), random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKFBOUT_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT0_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT1_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT2_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT3_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT4_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT5_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT6_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
} }
modname = "my_MMCME2_ADV" modname = "my_MMCME2_ADV"