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Add all CLKOUT1_DIVIDE bits 

Signed-off-by: Mitja Kleider <mitja@kleider.name>
This commit is contained in:
Mitja Kleider 2019-01-05 22:59:54 +01:00
parent 7f17e85307
commit 540999acdf
3 changed files with 62 additions and 27 deletions
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2
fuzzers/031-mmcm/Makefile
View File

@ -1,6 +1,6 @@
# read/write width is relatively slow to resolve
# Even slower with multi bit masks...
N := 8
N := 14
include ../fuzzer.mk
SEGDATAS=$(addsuffix /segdata_cmt_top_r_lower_b.txt,$(SPECIMENS))

46
fuzzers/031-mmcm/generate.py
View File

@ -7,22 +7,40 @@ from prjxray import verilog
def clkout_tags(segmk, ps, site):
""" Notes:
First bit is only active for value 1, for 1-128 in total 14 bits are toggling.
The relation is not clear yet, multiplication of the value by 2 does not fully correlate.
"""
Special bit for value 1 (bypass), all bits off for value 128.
Two 7 bit counters, sharing LSB (one counter is value+1, inverting the LSB).
"""
for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]:
# 1-128 => 0-127 for actual 7 bit value
paramadj = 2 * int(ps[param])
bitstr = [int(x) for x in "{0:08b}".format(paramadj)[::-1]]
# FIXME: only bits 0 and 1 resolving
for i in range(8):
# for i in range(2):
#if i in [0, 3, 5]:
# mybit = 1 ^ bitstr[i]
#else:
value = int(ps[param])
# bypass bit
segmk.add_site_tag(site, '%s_NODIV' % param, value == 1)
bitstr = [int(x) for x in "{0:08b}".format(value)[::-1]]
bitstr2 = [int(x) for x in "{0:08b}".format(value + 1)[::-1]]
for i in range(7):
mybit = bitstr[i]
segmk.add_site_tag(site, '%s[%u]' % (param, i), mybit)
mybit2 = bitstr2[i]
if i == 0:
# shared (inverted) LSB
mybit2 = 1 ^ bitstr2[i]
assert mybit == mybit2, "{} value {} has invalid bit0 at".format(
param, value)
# special cases
if value == 1:
if i == 0:
mybit = 0
mybit2 = 0
elif i == 1:
mybit = 1
elif value == 128:
mybit = 0
mybit2 = 0
segmk.add_site_tag(site, '%s_CNT0_[%u]' % (param, i), mybit)
segmk.add_site_tag(site, '%s_CNT1_[%u]' % (param, i), mybit2)
def misc_tags(segmk, ps, site):
@ -54,7 +72,7 @@ def run():
assert j['module'] == 'my_MMCME2_ADV'
site = verilog.unquote(ps['LOC'])
#clkout_tags(segmk, ps, site)
clkout_tags(segmk, ps, site)
misc_tags(segmk, ps, site)
segmk.compile()

41
fuzzers/031-mmcm/top.py
View File

@ -6,6 +6,7 @@ from prjxray import verilog
from prjxray.verilog import vrandbit, vrandbits
import sys
import json
import numpy as np
def gen_sites():
@ -36,18 +37,34 @@ for loci, site in enumerate(sites):
}
params = {
"CLKOUT1_DIVIDE": random.randint(1, 128),
"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT4_CASCADE": random.choice(["\"TRUE\"", "\"FALSE\""]),
"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKFBOUT_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT0_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT1_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT2_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT3_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT4_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT5_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT6_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT1_DIVIDE":
int(
np.random.choice(
[1, 63, 127, 128, random.randint(2, 127)],
p=[0.2, 0.1, 0.1, 0.1,
0.5])), # make sure that special values are present
"STARTUP_WAIT":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT4_CASCADE":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"STARTUP_WAIT":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKFBOUT_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT0_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT1_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT2_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT3_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT4_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT5_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT6_USE_FINE_PS":
random.choice(["\"TRUE\"", "\"FALSE\""]),
}
modname = "my_MMCME2_ADV"