mirror of https://github.com/openXC7/prjxray.git
Rename SegmentType to BlockType.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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@ -92,7 +92,7 @@ class FasmAssembler(object):
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gridinfo = self.grid.gridinfo_at_tilename(tile)
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gridinfo = self.grid.gridinfo_at_tilename(tile)
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# TODO: How to determine if the feature targets BLOCK_RAM segment type?
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# TODO: How to determine if the feature targets BLOCK_RAM segment type?
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bits = gridinfo.bits[grid.SegmentType.CLB_IO_CLK]
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bits = gridinfo.bits[grid.BlockType.CLB_IO_CLK]
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seg_baseaddr = bits.base_address
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seg_baseaddr = bits.base_address
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seg_word_base = bits.offset
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seg_word_base = bits.offset
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@ -3,11 +3,11 @@ import enum
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from prjxray import segment_map
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from prjxray import segment_map
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class SegmentType(enum.Enum):
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class BlockType(enum.Enum):
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# Segments describing CLB features, interconnect, clocks and IOs.
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# Frames describing CLB features, interconnect, clocks and IOs.
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CLB_IO_CLK = 'CLB_IO_CLK'
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CLB_IO_CLK = 'CLB_IO_CLK'
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# Segments describing block RAM initialization.
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# Frames describing block RAM initialization.
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BLOCK_RAM = 'BLOCK_RAM'
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BLOCK_RAM = 'BLOCK_RAM'
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@ -58,7 +58,7 @@ class Grid(object):
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if 'bits' in tileinfo:
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if 'bits' in tileinfo:
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for k in tileinfo['bits']:
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for k in tileinfo['bits']:
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segment_type = SegmentType(k)
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segment_type = BlockType(k)
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base_address = int(tileinfo['bits'][k]['baseaddr'], 0)
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base_address = int(tileinfo['bits'][k]['baseaddr'], 0)
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bits[segment_type] = Bits(
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bits[segment_type] = Bits(
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base_address=base_address,
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base_address=base_address,
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