diff --git a/prjxray/fasm_assembler.py b/prjxray/fasm_assembler.py
index 7a69f882..c625ac6c 100644
--- a/prjxray/fasm_assembler.py
+++ b/prjxray/fasm_assembler.py
@@ -92,7 +92,7 @@ class FasmAssembler(object):
         gridinfo = self.grid.gridinfo_at_tilename(tile)
 
         # TODO: How to determine if the feature targets BLOCK_RAM segment type?
-        bits = gridinfo.bits[grid.SegmentType.CLB_IO_CLK]
+        bits = gridinfo.bits[grid.BlockType.CLB_IO_CLK]
 
         seg_baseaddr = bits.base_address
         seg_word_base = bits.offset
diff --git a/prjxray/grid.py b/prjxray/grid.py
index a31318ee..15b7c94d 100644
--- a/prjxray/grid.py
+++ b/prjxray/grid.py
@@ -3,11 +3,11 @@ import enum
 from prjxray import segment_map
 
 
-class SegmentType(enum.Enum):
-    # Segments describing CLB features, interconnect, clocks and IOs.
+class BlockType(enum.Enum):
+    # Frames describing CLB features, interconnect, clocks and IOs.
     CLB_IO_CLK = 'CLB_IO_CLK'
 
-    # Segments describing block RAM initialization.
+    # Frames describing block RAM initialization.
     BLOCK_RAM = 'BLOCK_RAM'
 
 
@@ -58,7 +58,7 @@ class Grid(object):
 
             if 'bits' in tileinfo:
                 for k in tileinfo['bits']:
-                    segment_type = SegmentType(k)
+                    segment_type = BlockType(k)
                     base_address = int(tileinfo['bits'][k]['baseaddr'], 0)
                     bits[segment_type] = Bits(
                         base_address=base_address,