mirror of https://github.com/openXC7/prjxray.git
Rename SegmentType to BlockType.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
parent
204c6246ad
commit
db5c8d0063
|
|
@ -92,7 +92,7 @@ class FasmAssembler(object):
|
|||
gridinfo = self.grid.gridinfo_at_tilename(tile)
|
||||
|
||||
# TODO: How to determine if the feature targets BLOCK_RAM segment type?
|
||||
bits = gridinfo.bits[grid.SegmentType.CLB_IO_CLK]
|
||||
bits = gridinfo.bits[grid.BlockType.CLB_IO_CLK]
|
||||
|
||||
seg_baseaddr = bits.base_address
|
||||
seg_word_base = bits.offset
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@ import enum
|
|||
from prjxray import segment_map
|
||||
|
||||
|
||||
class SegmentType(enum.Enum):
|
||||
# Segments describing CLB features, interconnect, clocks and IOs.
|
||||
class BlockType(enum.Enum):
|
||||
# Frames describing CLB features, interconnect, clocks and IOs.
|
||||
CLB_IO_CLK = 'CLB_IO_CLK'
|
||||
|
||||
# Segments describing block RAM initialization.
|
||||
# Frames describing block RAM initialization.
|
||||
BLOCK_RAM = 'BLOCK_RAM'
|
||||
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ class Grid(object):
|
|||
|
||||
if 'bits' in tileinfo:
|
||||
for k in tileinfo['bits']:
|
||||
segment_type = SegmentType(k)
|
||||
segment_type = BlockType(k)
|
||||
base_address = int(tileinfo['bits'][k]['baseaddr'], 0)
|
||||
bits[segment_type] = Bits(
|
||||
base_address=base_address,
|
||||
|
|
|
|||
Loading…
Reference in New Issue