mirror of https://github.com/openXC7/prjxray.git
Merge pull request #160 from mcmasterg/addtag
fuzzers: fix addtag regression
This commit is contained in:
John Mcmaster
GitHub
commit
cbc7e23d6d
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@ -92,29 +92,29 @@ with open("design.txt", "r") as f:
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is5 = '5' in ff_name
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if used:
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segmk.addtag(site, "%s.ZINI" % ff_name, 1 ^ init)
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segmk.add_site_tag(site, "%s.ZINI" % ff_name, 1 ^ init)
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# CLKINV turns out to be more complicated than origianlly thought
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if isff(cel_prim):
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segmk.addtag(site, "CLKINV", cinv)
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segmk.add_site_tag(site, "CLKINV", cinv)
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else:
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segmk.addtag(site, "CLKINV", 1 ^ cinv)
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segmk.add_site_tag(site, "CLKINV", 1 ^ cinv)
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# Synchronous vs asynchronous FF
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# Unlike most bits, shared between all CLB FFs
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segmk.addtag(site, "FFSYNC", cel_prim in ('FDSE', 'FDRE'))
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segmk.add_site_tag(site, "FFSYNC", cel_prim in ('FDSE', 'FDRE'))
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# Latch bit
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# Only applies to LUT6 (non-5) FF's
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if not is5:
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segmk.addtag(site, "LATCH", isl(cel_prim))
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segmk.add_site_tag(site, "LATCH", isl(cel_prim))
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'''
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On name:
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The primitives you listed have a control input to set the FF value to zero (clear/reset),
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the other three primitives have a control input that sets the FF value to one.
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Z => inversion
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'''
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segmk.addtag(
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segmk.add_site_tag(
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site, "%s.ZRST" % ff_name,
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cel_prim in ('FDRE', 'FDCE', 'LDCE'))
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@ -26,7 +26,7 @@ for l in f:
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# Theory: there is one bit for each mux positon
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# In each config 3 muxes are in one position, other 3 are in another
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inv = int(i == n)
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segmk.addtag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv)
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segmk.addtag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv)
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segmk.add_site_tag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv)
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segmk.add_site_tag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv)
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segmk.compile()
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segmk.write()
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@ -23,6 +23,6 @@ for l in f:
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which = bel[0]
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# One bit, set on O5
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segmk.addtag(loc, "CARRY4.%cCY0" % which, module == 'clb_NCY0_O5')
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segmk.add_site_tag(loc, "CARRY4.%cCY0" % which, module == 'clb_NCY0_O5')
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segmk.compile()
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segmk.write()
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@ -26,7 +26,7 @@ for l in f:
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# parameter nFORCE_R0=1;
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# .CE(din[0] | FORCE_CE1),
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# .R(din[1] & nFORCE_R0),
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segmk.addtag(site, "CEUSEDMUX", ce ^ 1)
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segmk.addtag(site, "SRUSEDMUX", r)
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segmk.add_site_tag(site, "CEUSEDMUX", ce ^ 1)
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segmk.add_site_tag(site, "SRUSEDMUX", r)
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segmk.compile()
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segmk.write()
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@ -53,7 +53,7 @@ for l in f:
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# add the 1-tag for this connection
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tag = "%sFFMUX.%s" % (which, src)
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segmk.addtag(loc, tag, 1)
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segmk.add_site_tag(loc, tag, 1)
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# remove this MUX from the cache, preventing generation of 0-tags for this MUX
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cache[loc].remove(which)
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@ -66,7 +66,7 @@ for loc, muxes in cache.items():
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if src == "F8" and which not in "B": continue
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if src == "AX": src = which + "X"
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tag = "%sFFMUX.%s" % (which, src)
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segmk.addtag(loc, tag, 0)
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segmk.add_site_tag(loc, tag, 0)
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# we know that all bits for those MUXes are in frames 30 and 31, so filter all other bits
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@ -53,7 +53,7 @@ for l in f:
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# add the 1-tag for this connection
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tag = "%sOUTMUX.%s" % (which, src)
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segmk.addtag(loc, tag, 1)
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segmk.add_site_tag(loc, tag, 1)
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# remove this MUX from the cache, preventing generation of 0-tags for this MUX
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cache[loc].remove(which)
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@ -66,7 +66,7 @@ for loc, muxes in cache.items():
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if src == "F8" and which not in "B": continue
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if src == "5Q": src = which + "5Q"
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tag = "%sOUTMUX.%s" % (which, src)
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segmk.addtag(loc, tag, 0)
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segmk.add_site_tag(loc, tag, 0)
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def bitfilter(frame_idx, bit_idx):
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@ -24,7 +24,7 @@ for l in f:
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'''
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srcs = ('0', '1', 'AX', 'CIN')
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for asrc in srcs:
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segmk.addtag(loc, "PRECYINIT.%s" % asrc, int(src == asrc))
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segmk.add_site_tag(loc, "PRECYINIT.%s" % asrc, int(src == asrc))
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segmk.compile()
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segmk.write()
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@ -40,10 +40,10 @@ for l in f:
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l = l.strip()
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module, loc, p0, p1, p2, p3 = l.split(',')
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segmk.addtag(
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segmk.add_site_tag(
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loc, "WA7USED",
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module in ('my_RAM128X1D', 'my_RAM128X1S', 'my_RAM256X1S'))
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segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S')
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segmk.add_site_tag(loc, "WA8USED", module == 'my_RAM256X1S')
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# (a, b, c, d)
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# Size set for RAM32X1S, RAM32X1D, and SRL16E
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@ -59,7 +59,8 @@ for l in f:
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# Clock Enable (CE) clock gate only enabled if we have clocked elements
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# A pure LUT6 does not, but everything else should
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segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])
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segmk.add_site_tag(
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loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])
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beli = 0
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for which, bel in zip('ABCD', bels):
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@ -123,10 +124,10 @@ for l in f:
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# Now commit bits after marking 1's
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for beli, bel in enumerate('ABCD'):
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segmk.addtag(loc, "%sLUT.RAM" % bel, ram[beli])
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segmk.addtag(loc, "%sLUT.SRL" % bel, srl[beli])
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segmk.add_site_tag(loc, "%sLUT.RAM" % bel, ram[beli])
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segmk.add_site_tag(loc, "%sLUT.SRL" % bel, srl[beli])
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# FIXME
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module == segmk.addtag(loc, "%sLUT.SMALL" % bel, size[beli])
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module == segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli])
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def bitfilter(frame_idx, bit_idx):
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@ -27,9 +27,9 @@ for l in f:
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c31 = int(c31)
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b31 = int(b31)
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a31 = int(a31)
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segmk.addtag(loc, "ADI1MUX.AI", 1 ^ a31)
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segmk.addtag(loc, "BDI1MUX.BI", 1 ^ b31)
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segmk.addtag(loc, "CDI1MUX.CI", 1 ^ c31)
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segmk.add_site_tag(loc, "ADI1MUX.AI", 1 ^ a31)
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segmk.add_site_tag(loc, "BDI1MUX.BI", 1 ^ b31)
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segmk.add_site_tag(loc, "CDI1MUX.CI", 1 ^ c31)
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segmk.compile()
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segmk.write()
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@ -53,9 +53,9 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile()
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segmk.write()
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@ -53,9 +53,9 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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def bitfilter(frame_idx, bit_idx):
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@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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def bitfilter(frame_idx, bit_idx):
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@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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def bitfilter(frame_idx, bit_idx):
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@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile()
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segmk.write()
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@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile()
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segmk.write()
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@ -60,9 +60,9 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile()
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segmk.write()
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@ -36,9 +36,9 @@ for tile, pips_nodes in tiledata.items():
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for dst, src in pipdata:
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if (dst, src) in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in nodes and src not in nodes:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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def bitfilter(frame_idx, bit_idx):
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@ -37,16 +37,16 @@ for arg in sys.argv[1:]:
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tile_type, pip = pip.split(".")
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src, dst = pip.split("->>")
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tag = "%s.%s" % (dst, src)
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segmk.addtag(tile, tag, 1)
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segmk.add_tile_tag(tile, tag, 1)
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if "HCLK_CK_BUFH" in src:
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en_tag = "ENABLE_BUFFER.%s" % src
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segmk.addtag(tile, en_tag, 1)
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segmk.add_tile_tag(tile, en_tag, 1)
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for tag, tag_dst in tags.items():
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if tag_dst != dst:
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segmk.addtag(tile, tag, 0)
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segmk.add_tile_tag(tile, tag, 0)
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for en_tag, en_tag_src in en_tags.items():
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if en_tag_src != src:
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segmk.addtag(tile, en_tag, 0)
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segmk.add_tile_tag(tile, en_tag, 0)
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segmk.compile()
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segmk.write(arg)
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@ -20,8 +20,9 @@ with open("design_%s.txt" % sys.argv[1], "r") as f:
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pattern = int(pattern.replace("48'h", ""), 16)
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for i in range(48):
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segmk.addtag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1)
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segmk.addtag(tile, "%s.PATTERN[%d]" % (dsp, i), (pattern >> i) & 1)
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segmk.add_tile_tag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1)
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segmk.add_tile_tag(
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tile, "%s.PATTERN[%d]" % (dsp, i), (pattern >> i) & 1)
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segmk.compile()
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segmk.write(suffix=sys.argv[1])
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