From 37c446b2551ee4f156ac1913c26c05e116ead22d Mon Sep 17 00:00:00 2001 From: John McMaster Date: Wed, 17 Oct 2018 20:11:20 -0700 Subject: [PATCH] fuzzers: fix addtag regression Signed-off-by: John McMaster --- fuzzers/011-ffconfig/generate.py | 12 ++++++------ fuzzers/012-clbn5ffmux/generate.py | 4 ++-- fuzzers/013-clbncy0/generate.py | 2 +- fuzzers/014-ffsrcemux/generate.py | 4 ++-- fuzzers/015-clbnffmux/generate.py | 4 ++-- fuzzers/016-clbnoutmux/generate.py | 4 ++-- fuzzers/017-clbprecyinit/generate.py | 2 +- fuzzers/018-clbram/generate.py | 13 +++++++------ fuzzers/019-ndi1mux/generate.py | 6 +++--- fuzzers/050-intpips/generate.py | 4 ++-- fuzzers/051-imuxlout/generate.py | 4 ++-- fuzzers/052-clkin/generate.py | 4 ++-- fuzzers/053-ctrlin/generate.py | 4 ++-- fuzzers/054-gfan/generate.py | 4 ++-- fuzzers/055-gnd/generate.py | 4 ++-- fuzzers/056-rempips/generate.py | 4 ++-- fuzzers/057-bipips/generate.py | 4 ++-- fuzzers/058-hclkpips/generate.py | 8 ++++---- fuzzers/100-dsp-mskpat/generate.py | 5 +++-- 19 files changed, 49 insertions(+), 47 deletions(-) diff --git a/fuzzers/011-ffconfig/generate.py b/fuzzers/011-ffconfig/generate.py index 3510e0f9..f38abcac 100644 --- a/fuzzers/011-ffconfig/generate.py +++ b/fuzzers/011-ffconfig/generate.py @@ -92,29 +92,29 @@ with open("design.txt", "r") as f: is5 = '5' in ff_name if used: - segmk.addtag(site, "%s.ZINI" % ff_name, 1 ^ init) + segmk.add_site_tag(site, "%s.ZINI" % ff_name, 1 ^ init) # CLKINV turns out to be more complicated than origianlly thought if isff(cel_prim): - segmk.addtag(site, "CLKINV", cinv) + segmk.add_site_tag(site, "CLKINV", cinv) else: - segmk.addtag(site, "CLKINV", 1 ^ cinv) + segmk.add_site_tag(site, "CLKINV", 1 ^ cinv) # Synchronous vs asynchronous FF # Unlike most bits, shared between all CLB FFs - segmk.addtag(site, "FFSYNC", cel_prim in ('FDSE', 'FDRE')) + segmk.add_site_tag(site, "FFSYNC", cel_prim in ('FDSE', 'FDRE')) # Latch bit # Only applies to LUT6 (non-5) FF's if not is5: - segmk.addtag(site, "LATCH", isl(cel_prim)) + segmk.add_site_tag(site, "LATCH", isl(cel_prim)) ''' On name: The primitives you listed have a control input to set the FF value to zero (clear/reset), the other three primitives have a control input that sets the FF value to one. Z => inversion ''' - segmk.addtag( + segmk.add_site_tag( site, "%s.ZRST" % ff_name, cel_prim in ('FDRE', 'FDCE', 'LDCE')) diff --git a/fuzzers/012-clbn5ffmux/generate.py b/fuzzers/012-clbn5ffmux/generate.py index e2e5a7d9..cdcad726 100644 --- a/fuzzers/012-clbn5ffmux/generate.py +++ b/fuzzers/012-clbn5ffmux/generate.py @@ -26,7 +26,7 @@ for l in f: # Theory: there is one bit for each mux positon # In each config 3 muxes are in one position, other 3 are in another inv = int(i == n) - segmk.addtag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv) - segmk.addtag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv) + segmk.add_site_tag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv) + segmk.add_site_tag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv) segmk.compile() segmk.write() diff --git a/fuzzers/013-clbncy0/generate.py b/fuzzers/013-clbncy0/generate.py index b3703363..9408cbbd 100644 --- a/fuzzers/013-clbncy0/generate.py +++ b/fuzzers/013-clbncy0/generate.py @@ -23,6 +23,6 @@ for l in f: which = bel[0] # One bit, set on O5 - segmk.addtag(loc, "CARRY4.%cCY0" % which, module == 'clb_NCY0_O5') + segmk.add_site_tag(loc, "CARRY4.%cCY0" % which, module == 'clb_NCY0_O5') segmk.compile() segmk.write() diff --git a/fuzzers/014-ffsrcemux/generate.py b/fuzzers/014-ffsrcemux/generate.py index befda57c..351f4917 100644 --- a/fuzzers/014-ffsrcemux/generate.py +++ b/fuzzers/014-ffsrcemux/generate.py @@ -26,7 +26,7 @@ for l in f: # parameter nFORCE_R0=1; # .CE(din[0] | FORCE_CE1), # .R(din[1] & nFORCE_R0), - segmk.addtag(site, "CEUSEDMUX", ce ^ 1) - segmk.addtag(site, "SRUSEDMUX", r) + segmk.add_site_tag(site, "CEUSEDMUX", ce ^ 1) + segmk.add_site_tag(site, "SRUSEDMUX", r) segmk.compile() segmk.write() diff --git a/fuzzers/015-clbnffmux/generate.py b/fuzzers/015-clbnffmux/generate.py index 79b49912..0b4de44d 100644 --- a/fuzzers/015-clbnffmux/generate.py +++ b/fuzzers/015-clbnffmux/generate.py @@ -53,7 +53,7 @@ for l in f: # add the 1-tag for this connection tag = "%sFFMUX.%s" % (which, src) - segmk.addtag(loc, tag, 1) + segmk.add_site_tag(loc, tag, 1) # remove this MUX from the cache, preventing generation of 0-tags for this MUX cache[loc].remove(which) @@ -66,7 +66,7 @@ for loc, muxes in cache.items(): if src == "F8" and which not in "B": continue if src == "AX": src = which + "X" tag = "%sFFMUX.%s" % (which, src) - segmk.addtag(loc, tag, 0) + segmk.add_site_tag(loc, tag, 0) # we know that all bits for those MUXes are in frames 30 and 31, so filter all other bits diff --git a/fuzzers/016-clbnoutmux/generate.py b/fuzzers/016-clbnoutmux/generate.py index ede555f0..f206b044 100644 --- a/fuzzers/016-clbnoutmux/generate.py +++ b/fuzzers/016-clbnoutmux/generate.py @@ -53,7 +53,7 @@ for l in f: # add the 1-tag for this connection tag = "%sOUTMUX.%s" % (which, src) - segmk.addtag(loc, tag, 1) + segmk.add_site_tag(loc, tag, 1) # remove this MUX from the cache, preventing generation of 0-tags for this MUX cache[loc].remove(which) @@ -66,7 +66,7 @@ for loc, muxes in cache.items(): if src == "F8" and which not in "B": continue if src == "5Q": src = which + "5Q" tag = "%sOUTMUX.%s" % (which, src) - segmk.addtag(loc, tag, 0) + segmk.add_site_tag(loc, tag, 0) def bitfilter(frame_idx, bit_idx): diff --git a/fuzzers/017-clbprecyinit/generate.py b/fuzzers/017-clbprecyinit/generate.py index 5da0f0b9..46e2f506 100644 --- a/fuzzers/017-clbprecyinit/generate.py +++ b/fuzzers/017-clbprecyinit/generate.py @@ -24,7 +24,7 @@ for l in f: ''' srcs = ('0', '1', 'AX', 'CIN') for asrc in srcs: - segmk.addtag(loc, "PRECYINIT.%s" % asrc, int(src == asrc)) + segmk.add_site_tag(loc, "PRECYINIT.%s" % asrc, int(src == asrc)) segmk.compile() segmk.write() diff --git a/fuzzers/018-clbram/generate.py b/fuzzers/018-clbram/generate.py index 88b99c81..3f69170d 100644 --- a/fuzzers/018-clbram/generate.py +++ b/fuzzers/018-clbram/generate.py @@ -40,10 +40,10 @@ for l in f: l = l.strip() module, loc, p0, p1, p2, p3 = l.split(',') - segmk.addtag( + segmk.add_site_tag( loc, "WA7USED", module in ('my_RAM128X1D', 'my_RAM128X1S', 'my_RAM256X1S')) - segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S') + segmk.add_site_tag(loc, "WA8USED", module == 'my_RAM256X1S') # (a, b, c, d) # Size set for RAM32X1S, RAM32X1D, and SRL16E @@ -59,7 +59,8 @@ for l in f: # Clock Enable (CE) clock gate only enabled if we have clocked elements # A pure LUT6 does not, but everything else should - segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6']) + segmk.add_site_tag( + loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6']) beli = 0 for which, bel in zip('ABCD', bels): @@ -123,10 +124,10 @@ for l in f: # Now commit bits after marking 1's for beli, bel in enumerate('ABCD'): - segmk.addtag(loc, "%sLUT.RAM" % bel, ram[beli]) - segmk.addtag(loc, "%sLUT.SRL" % bel, srl[beli]) + segmk.add_site_tag(loc, "%sLUT.RAM" % bel, ram[beli]) + segmk.add_site_tag(loc, "%sLUT.SRL" % bel, srl[beli]) # FIXME - module == segmk.addtag(loc, "%sLUT.SMALL" % bel, size[beli]) + module == segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli]) def bitfilter(frame_idx, bit_idx): diff --git a/fuzzers/019-ndi1mux/generate.py b/fuzzers/019-ndi1mux/generate.py index 84738272..ff3e8800 100644 --- a/fuzzers/019-ndi1mux/generate.py +++ b/fuzzers/019-ndi1mux/generate.py @@ -27,9 +27,9 @@ for l in f: c31 = int(c31) b31 = int(b31) a31 = int(a31) - segmk.addtag(loc, "ADI1MUX.AI", 1 ^ a31) - segmk.addtag(loc, "BDI1MUX.BI", 1 ^ b31) - segmk.addtag(loc, "CDI1MUX.CI", 1 ^ c31) + segmk.add_site_tag(loc, "ADI1MUX.AI", 1 ^ a31) + segmk.add_site_tag(loc, "BDI1MUX.BI", 1 ^ b31) + segmk.add_site_tag(loc, "CDI1MUX.CI", 1 ^ c31) segmk.compile() segmk.write() diff --git a/fuzzers/050-intpips/generate.py b/fuzzers/050-intpips/generate.py index 4e6f261f..8214bf92 100644 --- a/fuzzers/050-intpips/generate.py +++ b/fuzzers/050-intpips/generate.py @@ -53,9 +53,9 @@ for tile, pips_srcs_dsts in tiledata.items(): if pip in ignpip: pass elif pip in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif src_dst[1] not in dsts: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) segmk.compile() segmk.write() diff --git a/fuzzers/051-imuxlout/generate.py b/fuzzers/051-imuxlout/generate.py index 36b63abc..f1da9e1d 100644 --- a/fuzzers/051-imuxlout/generate.py +++ b/fuzzers/051-imuxlout/generate.py @@ -53,9 +53,9 @@ for tile, pips_srcs_dsts in tiledata.items(): if pip in ignpip: pass elif pip in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif src_dst[1] not in dsts: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) def bitfilter(frame_idx, bit_idx): diff --git a/fuzzers/052-clkin/generate.py b/fuzzers/052-clkin/generate.py index 45088648..89c0365e 100644 --- a/fuzzers/052-clkin/generate.py +++ b/fuzzers/052-clkin/generate.py @@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items(): if pip in ignpip: pass elif pip in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif src_dst[1] not in dsts: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) def bitfilter(frame_idx, bit_idx): diff --git a/fuzzers/053-ctrlin/generate.py b/fuzzers/053-ctrlin/generate.py index b428fc6c..1a576c4a 100644 --- a/fuzzers/053-ctrlin/generate.py +++ b/fuzzers/053-ctrlin/generate.py @@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items(): if pip in ignpip: pass elif pip in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif src_dst[1] not in dsts: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) def bitfilter(frame_idx, bit_idx): diff --git a/fuzzers/054-gfan/generate.py b/fuzzers/054-gfan/generate.py index 943102d4..4162f4c7 100644 --- a/fuzzers/054-gfan/generate.py +++ b/fuzzers/054-gfan/generate.py @@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items(): if pip in ignpip: pass elif pip in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif src_dst[1] not in dsts: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) segmk.compile() segmk.write() diff --git a/fuzzers/055-gnd/generate.py b/fuzzers/055-gnd/generate.py index f358974d..bfd31409 100644 --- a/fuzzers/055-gnd/generate.py +++ b/fuzzers/055-gnd/generate.py @@ -50,9 +50,9 @@ for tile, pips_srcs_dsts in tiledata.items(): if pip in ignpip: pass elif pip in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif src_dst[1] not in dsts: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) segmk.compile() segmk.write() diff --git a/fuzzers/056-rempips/generate.py b/fuzzers/056-rempips/generate.py index 5304ec88..72b0d5eb 100644 --- a/fuzzers/056-rempips/generate.py +++ b/fuzzers/056-rempips/generate.py @@ -60,9 +60,9 @@ for tile, pips_srcs_dsts in tiledata.items(): if pip in ignpip: pass elif pip in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif src_dst[1] not in dsts: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) segmk.compile() segmk.write() diff --git a/fuzzers/057-bipips/generate.py b/fuzzers/057-bipips/generate.py index e27b57a1..abbed6df 100644 --- a/fuzzers/057-bipips/generate.py +++ b/fuzzers/057-bipips/generate.py @@ -36,9 +36,9 @@ for tile, pips_nodes in tiledata.items(): for dst, src in pipdata: if (dst, src) in pips: - segmk.addtag(tile, "%s.%s" % (dst, src), 1) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) elif dst not in nodes and src not in nodes: - segmk.addtag(tile, "%s.%s" % (dst, src), 0) + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) def bitfilter(frame_idx, bit_idx): diff --git a/fuzzers/058-hclkpips/generate.py b/fuzzers/058-hclkpips/generate.py index c51d1a52..230a624f 100644 --- a/fuzzers/058-hclkpips/generate.py +++ b/fuzzers/058-hclkpips/generate.py @@ -37,16 +37,16 @@ for arg in sys.argv[1:]: tile_type, pip = pip.split(".") src, dst = pip.split("->>") tag = "%s.%s" % (dst, src) - segmk.addtag(tile, tag, 1) + segmk.add_tile_tag(tile, tag, 1) if "HCLK_CK_BUFH" in src: en_tag = "ENABLE_BUFFER.%s" % src - segmk.addtag(tile, en_tag, 1) + segmk.add_tile_tag(tile, en_tag, 1) for tag, tag_dst in tags.items(): if tag_dst != dst: - segmk.addtag(tile, tag, 0) + segmk.add_tile_tag(tile, tag, 0) for en_tag, en_tag_src in en_tags.items(): if en_tag_src != src: - segmk.addtag(tile, en_tag, 0) + segmk.add_tile_tag(tile, en_tag, 0) segmk.compile() segmk.write(arg) diff --git a/fuzzers/100-dsp-mskpat/generate.py b/fuzzers/100-dsp-mskpat/generate.py index 989ade12..10ae87d9 100644 --- a/fuzzers/100-dsp-mskpat/generate.py +++ b/fuzzers/100-dsp-mskpat/generate.py @@ -20,8 +20,9 @@ with open("design_%s.txt" % sys.argv[1], "r") as f: pattern = int(pattern.replace("48'h", ""), 16) for i in range(48): - segmk.addtag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1) - segmk.addtag(tile, "%s.PATTERN[%d]" % (dsp, i), (pattern >> i) & 1) + segmk.add_tile_tag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1) + segmk.add_tile_tag( + tile, "%s.PATTERN[%d]" % (dsp, i), (pattern >> i) & 1) segmk.compile() segmk.write(suffix=sys.argv[1])