mirror of https://github.com/openXC7/prjxray.git
Rick Altherr
GitHub
commit
c38907cd73
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@ -6,3 +6,4 @@
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/usage_statistics_webtalk.*
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/vivado*
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/design.txt
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/out_*
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@ -3,6 +3,7 @@ all:
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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rm -rf out_* *~
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.PHONY: all clean
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@ -10,3 +10,10 @@ There is no logic outside of the ROI in order to keep IOB to ROI delays short
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Its expected the end user will rip out everything inside the ROI
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To target Arty A7 you should source the artix DB environment script then source arty.sh
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To build the baseline harness:
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make
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To build a sample design using the harness:
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XRAY_ROIV=roi_inv.v make
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@ -1 +1,3 @@
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export XRAY_PART=xc7a35tcsg324-1
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export XRAY_PINCFG=ARTY-A7-SWBUT
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@ -0,0 +1,14 @@
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# XC7A35T-1CPG236C
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export XRAY_PART=xc7a35tcpg236-1
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export XRAY_PINCFG=BASYS3-SWBUT
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# For generating DB
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export XRAY_PIN_00="V17"
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export XRAY_PIN_01="V16"
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export XRAY_PIN_02="W16"
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export XRAY_PIN_03="W17"
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export XRAY_PIN_04="W15"
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export XRAY_PIN_05="V15"
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export XRAY_PIN_06="W14"
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export XRAY_BITREAD="$XRAY_DIR/build/tools/bitread -part_file $XRAY_DIR/database/artix7/xc7a35tcpg236-1.yaml"
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@ -0,0 +1,8 @@
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`ifndef DIN_N
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`define DIN_N 8
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`endif
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`ifndef DOUT_N
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`define DOUT_N 8
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`endif
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@ -0,0 +1,49 @@
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//See README and tcl for more info
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O());
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(1'b0),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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@ -0,0 +1,53 @@
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//Connect the switches to the LEDs, inverting the signal in the ROI
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//Assumes # inputs = # outputs
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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wire [DIN_N-1:0] internal;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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//Very expensive inverter
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(internal[i]));
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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//Very expensive buffer
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b010)
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) lut (
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.I0(internal[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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@ -1,6 +1,13 @@
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#!/bin/bash
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set -ex
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rm -f out_last
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vivado -mode batch -source runme.tcl
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test -z "$(fgrep CRITICAL vivado.log)"
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pushd out_last
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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${XRAY_SEGPRINT} -zd design.bits >design.segp
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${XRAY_DIR}/tools/segprint2fasm.py design.segp design.fasm
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${XRAY_DIR}/tools/fasm2frame.py design.fasm design.frm
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popd
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@ -32,17 +32,34 @@ set Y_DIN_BASE [expr "$Y_CLK_BASE + 1"]
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# Note: can actually go up one more if we want
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set Y_DOUT_BASE [expr "$XRAY_ROI_Y1 - $DIN_N * $PITCH"]
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set part "$::env(XRAY_PART)"
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set pincfg ""
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if { [info exists ::env(XRAY_PINCFG) ] } {
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set pincfg "$::env(XRAY_PINCFG)"
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}
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set roiv "roi_base.v"
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if { [info exists ::env(XRAY_ROIV) ] } {
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set roiv "$::env(XRAY_ROIV)"
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}
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set roiv_trim [string map {.v v} $roiv]
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set outdir "out_${part}_${pincfg}_${roiv_trim}"
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puts "Environment"
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puts " XRAY_ROI: $::env(XRAY_ROI)"
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puts " X_BASE: $X_BASE"
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puts " Y_DIN_BASE: $Y_DIN_BASE"
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puts " Y_CLK_BASE: $Y_CLK_BASE"
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puts " Y_DOUT_BASE: $Y_DOUT_BASE"
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puts " outdir: $outdir"
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file mkdir $outdir
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file link -symbolic out_last $outdir
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source ../../utils/utils.tcl
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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read_verilog $roiv
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# added flatten_hierarchy
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# dout_shr was getting folded into the pblock
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# synth_design -top top -flatten_hierarchy none -no_lc -keep_equivalent_registers -resource_sharing off
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@ -52,7 +69,6 @@ synth_design -top top -flatten_hierarchy none -verilog_define DIN_N=$DIN_N -veri
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array set net2pin [list]
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# Create pin assignments based on what we are targetting
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set part "$::env(XRAY_PART)"
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# A50T I/O Bank 16 sequential layout
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if {$part eq "xc7a50tfgg484-1"} {
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# Partial list, expand as needed
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@ -77,54 +93,84 @@ if {$part eq "xc7a50tfgg484-1"} {
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incr banki
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set net2pin(dout[$i]) $pin
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}
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# Arty A7 switch, button, and LED
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} elseif {$part eq "xc7a35tcsg324-1"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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# 4 switches then 4 buttons
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set sw_but "A8 C11 C10 A10 D9 C9 B9 B8"
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# 4 LEDs then 4 RGB LEDs (green only)
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set leds "H5 J5 T9 T10 F6 J4 J2 H6"
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# Arty A7 switch, button, and LED
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if {$pincfg eq "ARTY-A7-SWBUT"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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# 4 switches then 4 buttons
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set sw_but "A8 C11 C10 A10 D9 C9 B9 B8"
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# 4 LEDs then 4 RGB LEDs (green only)
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set leds "H5 J5 T9 T10 F6 J4 J2 H6"
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# 100 MHz CLK onboard
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set pin "E3"
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set net2pin(clk) $pin
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# 100 MHz CLK onboard
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set pin "E3"
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set net2pin(clk) $pin
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $sw_but $i]
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set net2pin(din[$i]) $pin
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $sw_but $i]
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set net2pin(din[$i]) $pin
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}
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
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}
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# Arty A7 pmod
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# Disabled per above
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} elseif {$pincfg eq "ARTY-A7-PMOD"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
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set pmod_jb "E15 E16 D15 C15 J17 J18 K15 J15"
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set pmod_jc "U12 V12 V10 V11 U14 V14 T13 U13"
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# CLK on Pmod JA
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set pin [lindex $pmod_ja 0]
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set net2pin(clk) $pin
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# DIN on Pmod JB
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $pmod_jb $i]
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set net2pin(din[$i]) $pin
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}
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# DOUT on Pmod JC
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $pmod_jc $i]
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set net2pin(dout[$i]) $pin
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}
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} else {
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error "Unsupported config $pincfg"
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}
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} elseif {$part eq "xc7a35tcpg236-1"} {
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if {$pincfg eq "BASYS3-SWBUT"} {
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# https://raw.githubusercontent.com/Digilent/digilent-xdc/master/Basys-3-Master.xdc
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
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}
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# Arty A7 pmod
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# Disabled per above
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} elseif {$part eq "xc7a35tcsg324-1"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
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set pmod_jb "E15 E16 D15 C15 J17 J18 K15 J15"
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set pmod_jc "U12 V12 V10 V11 U14 V14 T13 U13"
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# Slide switches
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set sws "V17 V16 W16 W17 W15 V15 W14 W13 V2 T3 T2 R3 W2 U1 T1 R2"
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set leds "U16 E19 U19 V19 W18 U15 U14 V14 V13 V3 W3 U3 P3 N3 P1 L1"
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# CLK on Pmod JA
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set pin [lindex $pmod_ja 0]
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set net2pin(clk) $pin
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# 100 MHz CLK onboard
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set pin "W5"
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set net2pin(clk) $pin
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# DIN on Pmod JB
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $pmod_jb $i]
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set net2pin(din[$i]) $pin
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $sws $i]
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set net2pin(din[$i]) $pin
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}
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
|
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}
|
||||
} else {
|
||||
error "Unsupported config $pincfg"
|
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}
|
||||
|
||||
# DOUT on Pmod JC
|
||||
for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $pmod_jc $i]
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set net2pin(dout[$i]) $pin
|
||||
}
|
||||
} else {
|
||||
error "Unsupported part $part"
|
||||
error "Pins: unsupported part $part"
|
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}
|
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|
||||
# Now actually apply the pin definitions
|
||||
|
|
@ -338,8 +384,11 @@ if {1} {
|
|||
} elseif {$part eq "xc7a35tcsg324-1"} {
|
||||
set node "INT_L_X10Y${y}/SW6BEG0"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
} elseif {$part eq "xc7a35tcpg236-1"} {
|
||||
set node "INT_L_X10Y${y}/SW6BEG0"
|
||||
route_via2 "roi/dout[$i]" "$node"
|
||||
} else {
|
||||
error "Unsupported part $part"
|
||||
error "Routing: unsupported part $part"
|
||||
}
|
||||
# XXX: only care about right ports on Arty
|
||||
} else {
|
||||
|
|
@ -357,6 +406,7 @@ close $fp
|
|||
puts "routing design"
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_checkpoint -force $outdir/design.dcp
|
||||
set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
|
||||
write_bitstream -force $outdir/design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,6 @@
|
|||
//See README and tcl for more info
|
||||
|
||||
`ifndef DIN_N
|
||||
`define DIN_N 4
|
||||
`endif
|
||||
|
||||
`ifndef DOUT_N
|
||||
`define DOUT_N 4
|
||||
`endif
|
||||
`include "defines.v"
|
||||
|
||||
module top(input wire clk,
|
||||
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
|
||||
|
|
@ -18,48 +12,3 @@ module top(input wire clk,
|
|||
.din(din), .dout(dout));
|
||||
endmodule
|
||||
|
||||
module roi(input clk,
|
||||
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
|
||||
parameter DIN_N = 4;
|
||||
parameter DOUT_N = 4;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
//CLK
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
reg clk_reg;
|
||||
always @(posedge clk) begin
|
||||
clk_reg <= clk_reg;
|
||||
end
|
||||
|
||||
//DIN
|
||||
for (i = 0; i < DIN_N; i = i+1) begin:ins
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 #(
|
||||
.INIT(64'b01)
|
||||
) lut (
|
||||
.I0(din[i]),
|
||||
.I1(1'b0),
|
||||
.I2(1'b0),
|
||||
.I3(1'b0),
|
||||
.I4(1'b0),
|
||||
.I5(1'b0),
|
||||
.O());
|
||||
end
|
||||
|
||||
//DOUT
|
||||
for (i = 0; i < DOUT_N; i = i+1) begin:outs
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 #(
|
||||
.INIT(64'b01)
|
||||
) lut (
|
||||
.I0(1'b0),
|
||||
.I1(1'b0),
|
||||
.I2(1'b0),
|
||||
.I3(1'b0),
|
||||
.I4(1'b0),
|
||||
.I5(1'b0),
|
||||
.O(dout[i]));
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -183,6 +183,7 @@ def run(f_in, f_out, sparse=False, debug=False):
|
|||
'INT_L': int2dbkey,
|
||||
'INT_R': int2dbkey,
|
||||
'HCLK_L': int2dbkey,
|
||||
'HCLK_R': int2dbkey,
|
||||
}
|
||||
|
||||
f = tile2dbkey.get(tilej['type'], None)
|
||||
|
|
|
|||
|
|
@ -61,10 +61,11 @@ def tag2fasm(grid, seg, tag):
|
|||
'INT_L': intf,
|
||||
'INT_R': intf,
|
||||
'HCLK_L': intf,
|
||||
'HCLK_R': intf,
|
||||
}
|
||||
f = tag2asm.get(tile_type, None)
|
||||
if f is None:
|
||||
raise Exception("Unhandled segment type %s" % tilej['type'])
|
||||
raise Exception("Unhandled segment type %s" % tile_type)
|
||||
return f(seg, tile, tag_post)
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue