diff --git a/minitests/roi_harness/.gitignore b/minitests/roi_harness/.gitignore
index 82a01aa0..dd262534 100644
--- a/minitests/roi_harness/.gitignore
+++ b/minitests/roi_harness/.gitignore
@@ -6,3 +6,4 @@
 /usage_statistics_webtalk.*
 /vivado*
 /design.txt
+/out_*
diff --git a/minitests/roi_harness/Makefile b/minitests/roi_harness/Makefile
index e9e022b0..a35796d1 100644
--- a/minitests/roi_harness/Makefile
+++ b/minitests/roi_harness/Makefile
@@ -3,6 +3,7 @@ all:
 
 clean:
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
+	rm -rf out_* *~
 
 .PHONY: all clean
 
diff --git a/minitests/roi_harness/README.txt b/minitests/roi_harness/README.txt
index c8fe8978..e2f90c13 100644
--- a/minitests/roi_harness/README.txt
+++ b/minitests/roi_harness/README.txt
@@ -10,3 +10,10 @@ There is no logic outside of the ROI in order to keep IOB to ROI delays short
 Its expected the end user will rip out everything inside the ROI
 
 To target Arty A7 you should source the artix DB environment script then source arty.sh
+
+To build the baseline harness:
+make
+
+To build a sample design using the harness:
+XRAY_ROIV=roi_inv.v make
+
diff --git a/minitests/roi_harness/arty.sh b/minitests/roi_harness/arty.sh
index 2b9b208c..ffcbd0b1 100644
--- a/minitests/roi_harness/arty.sh
+++ b/minitests/roi_harness/arty.sh
@@ -1 +1,3 @@
 export XRAY_PART=xc7a35tcsg324-1
+export XRAY_PINCFG=ARTY-A7-SWBUT
+
diff --git a/minitests/roi_harness/basys3.sh b/minitests/roi_harness/basys3.sh
new file mode 100644
index 00000000..00fed676
--- /dev/null
+++ b/minitests/roi_harness/basys3.sh
@@ -0,0 +1,14 @@
+# XC7A35T-1CPG236C
+export XRAY_PART=xc7a35tcpg236-1
+export XRAY_PINCFG=BASYS3-SWBUT
+
+# For generating DB
+export XRAY_PIN_00="V17"
+export XRAY_PIN_01="V16"
+export XRAY_PIN_02="W16"
+export XRAY_PIN_03="W17"
+export XRAY_PIN_04="W15"
+export XRAY_PIN_05="V15"
+export XRAY_PIN_06="W14"
+
+export XRAY_BITREAD="$XRAY_DIR/build/tools/bitread -part_file $XRAY_DIR/database/artix7/xc7a35tcpg236-1.yaml"
diff --git a/minitests/roi_harness/defines.v b/minitests/roi_harness/defines.v
new file mode 100644
index 00000000..1008d558
--- /dev/null
+++ b/minitests/roi_harness/defines.v
@@ -0,0 +1,8 @@
+`ifndef DIN_N
+`define DIN_N 8
+`endif
+
+`ifndef DOUT_N
+`define DOUT_N 8
+`endif
+
diff --git a/minitests/roi_harness/roi_base.v b/minitests/roi_harness/roi_base.v
new file mode 100644
index 00000000..a77662cc
--- /dev/null
+++ b/minitests/roi_harness/roi_base.v
@@ -0,0 +1,49 @@
+//See README and tcl for more info
+
+`include "defines.v"
+
+module roi(input clk,
+        input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
+    parameter DIN_N = `DIN_N;
+    parameter DOUT_N = `DOUT_N;
+
+    genvar i;
+    generate
+        //CLK
+        (* KEEP, DONT_TOUCH *)
+        reg clk_reg;
+        always @(posedge clk) begin
+            clk_reg <= clk_reg;
+        end
+
+        //DIN
+        for (i = 0; i < DIN_N; i = i+1) begin:ins
+            (* KEEP, DONT_TOUCH *)
+            LUT6 #(
+                .INIT(64'b01)
+            ) lut (
+                .I0(din[i]),
+                .I1(1'b0),
+                .I2(1'b0),
+                .I3(1'b0),
+                .I4(1'b0),
+                .I5(1'b0),
+                .O());
+        end
+
+        //DOUT
+        for (i = 0; i < DOUT_N; i = i+1) begin:outs
+            (* KEEP, DONT_TOUCH *)
+            LUT6 #(
+                .INIT(64'b01)
+            ) lut (
+                .I0(1'b0),
+                .I1(1'b0),
+                .I2(1'b0),
+                .I3(1'b0),
+                .I4(1'b0),
+                .I5(1'b0),
+                .O(dout[i]));
+        end
+    endgenerate
+endmodule
diff --git a/minitests/roi_harness/roi_inv.v b/minitests/roi_harness/roi_inv.v
new file mode 100644
index 00000000..7e575cb5
--- /dev/null
+++ b/minitests/roi_harness/roi_inv.v
@@ -0,0 +1,53 @@
+//Connect the switches to the LEDs, inverting the signal in the ROI
+//Assumes # inputs = # outputs
+
+`include "defines.v"
+
+module roi(input clk,
+        input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
+    parameter DIN_N = `DIN_N;
+    parameter DOUT_N = `DOUT_N;
+    wire [DIN_N-1:0] internal;
+
+    genvar i;
+    generate
+        //CLK
+        (* KEEP, DONT_TOUCH *)
+        reg clk_reg;
+        always @(posedge clk) begin
+            clk_reg <= clk_reg;
+        end
+
+        //DIN
+        for (i = 0; i < DIN_N; i = i+1) begin:ins
+            //Very expensive inverter
+            (* KEEP, DONT_TOUCH *)
+            LUT6 #(
+                .INIT(64'b01)
+            ) lut (
+                .I0(din[i]),
+                .I1(1'b0),
+                .I2(1'b0),
+                .I3(1'b0),
+                .I4(1'b0),
+                .I5(1'b0),
+                .O(internal[i]));
+        end
+
+        //DOUT
+        for (i = 0; i < DOUT_N; i = i+1) begin:outs
+            //Very expensive buffer
+            (* KEEP, DONT_TOUCH *)
+            LUT6 #(
+                .INIT(64'b010)
+            ) lut (
+                .I0(internal[i]),
+                .I1(1'b0),
+                .I2(1'b0),
+                .I3(1'b0),
+                .I4(1'b0),
+                .I5(1'b0),
+                .O(dout[i]));
+        end
+    endgenerate
+endmodule
diff --git a/minitests/roi_harness/runme.sh b/minitests/roi_harness/runme.sh
index 149ec619..a15ab84e 100644
--- a/minitests/roi_harness/runme.sh
+++ b/minitests/roi_harness/runme.sh
@@ -1,6 +1,13 @@
 #!/bin/bash
 
 set -ex
+rm -f out_last
 vivado -mode batch -source runme.tcl
 test -z "$(fgrep CRITICAL vivado.log)"
 
+pushd out_last
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
+${XRAY_SEGPRINT} -zd design.bits >design.segp
+${XRAY_DIR}/tools/segprint2fasm.py design.segp design.fasm
+${XRAY_DIR}/tools/fasm2frame.py design.fasm design.frm
+popd
diff --git a/minitests/roi_harness/runme.tcl b/minitests/roi_harness/runme.tcl
index 6d3b87c9..58e4d876 100644
--- a/minitests/roi_harness/runme.tcl
+++ b/minitests/roi_harness/runme.tcl
@@ -32,17 +32,34 @@ set Y_DIN_BASE [expr "$Y_CLK_BASE + 1"]
 # Note: can actually go up one more if we want
 set Y_DOUT_BASE [expr "$XRAY_ROI_Y1 - $DIN_N * $PITCH"]
 
+set part "$::env(XRAY_PART)"
+set pincfg ""
+if { [info exists ::env(XRAY_PINCFG) ] } {
+    set pincfg "$::env(XRAY_PINCFG)"
+}
+set roiv "roi_base.v"
+if { [info exists ::env(XRAY_ROIV) ] } {
+    set roiv "$::env(XRAY_ROIV)"
+}
+set roiv_trim [string map {.v v} $roiv]
+set outdir "out_${part}_${pincfg}_${roiv_trim}"
+
 puts "Environment"
 puts "  XRAY_ROI: $::env(XRAY_ROI)"
 puts "  X_BASE: $X_BASE"
 puts "  Y_DIN_BASE: $Y_DIN_BASE"
 puts "  Y_CLK_BASE: $Y_CLK_BASE"
 puts "  Y_DOUT_BASE: $Y_DOUT_BASE"
+puts "  outdir: $outdir"
+
+file mkdir $outdir
+file link -symbolic out_last $outdir
 
 source ../../utils/utils.tcl
 
 create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
+read_verilog $roiv
 # added flatten_hierarchy
 # dout_shr was getting folded into the pblock
 # synth_design -top top -flatten_hierarchy none -no_lc -keep_equivalent_registers -resource_sharing off
@@ -52,7 +69,6 @@ synth_design -top top -flatten_hierarchy none -verilog_define DIN_N=$DIN_N -veri
 array set net2pin [list]
 
 # Create pin assignments based on what we are targetting
-set part "$::env(XRAY_PART)"
 # A50T I/O Bank 16 sequential layout
 if {$part eq "xc7a50tfgg484-1"} {
     # Partial list, expand as needed
@@ -77,54 +93,84 @@ if {$part eq "xc7a50tfgg484-1"} {
         incr banki
         set net2pin(dout[$i]) $pin
    }
-# Arty A7 switch, button, and LED
 } elseif {$part eq "xc7a35tcsg324-1"} {
-    # https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
-    # 4 switches then 4 buttons
-    set sw_but "A8 C11 C10 A10  D9 C9 B9 B8"
-    # 4 LEDs then 4 RGB LEDs (green only)
-    set leds "H5 J5 T9 T10  F6 J4 J2 H6"
+    # Arty A7 switch, button, and LED
+    if {$pincfg eq "ARTY-A7-SWBUT"} {
+        # https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
+        # 4 switches then 4 buttons
+        set sw_but "A8 C11 C10 A10  D9 C9 B9 B8"
+        # 4 LEDs then 4 RGB LEDs (green only)
+        set leds "H5 J5 T9 T10  F6 J4 J2 H6"
 
-    # 100 MHz CLK onboard
-    set pin "E3"
-    set net2pin(clk) $pin
+        # 100 MHz CLK onboard
+        set pin "E3"
+        set net2pin(clk) $pin
 
-    # DIN
-    for {set i 0} {$i < $DIN_N} {incr i} {
-        set pin [lindex $sw_but $i]
-        set net2pin(din[$i]) $pin
+        # DIN
+        for {set i 0} {$i < $DIN_N} {incr i} {
+            set pin [lindex $sw_but $i]
+            set net2pin(din[$i]) $pin
+        }
+
+        # DOUT
+        for {set i 0} {$i < $DOUT_N} {incr i} {
+            set pin [lindex $leds $i]
+            set net2pin(dout[$i]) $pin
+       }
+    # Arty A7 pmod
+    # Disabled per above
+    } elseif {$pincfg eq "ARTY-A7-PMOD"} {
+        # https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
+        set pmod_ja "G13 B11 A11 D12  D13 B18 A18 K16"
+        set pmod_jb "E15 E16 D15 C15  J17 J18 K15 J15"
+        set pmod_jc "U12 V12 V10 V11  U14 V14 T13 U13"
+
+        # CLK on Pmod JA
+        set pin [lindex $pmod_ja 0]
+        set net2pin(clk) $pin
+
+        # DIN on Pmod JB
+        for {set i 0} {$i < $DIN_N} {incr i} {
+            set pin [lindex $pmod_jb $i]
+            set net2pin(din[$i]) $pin
+        }
+
+        # DOUT on Pmod JC
+        for {set i 0} {$i < $DOUT_N} {incr i} {
+            set pin [lindex $pmod_jc $i]
+            set net2pin(dout[$i]) $pin
+       }
+    } else {
+        error "Unsupported config $pincfg"
     }
+} elseif {$part eq "xc7a35tcpg236-1"} {
+    if {$pincfg eq "BASYS3-SWBUT"} {
+        # https://raw.githubusercontent.com/Digilent/digilent-xdc/master/Basys-3-Master.xdc
 
-    # DOUT
-    for {set i 0} {$i < $DOUT_N} {incr i} {
-        set pin [lindex $leds $i]
-        set net2pin(dout[$i]) $pin
-   }
-# Arty A7 pmod
-# Disabled per above
-} elseif {$part eq "xc7a35tcsg324-1"} {
-    # https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
-    set pmod_ja "G13 B11 A11 D12  D13 B18 A18 K16"
-    set pmod_jb "E15 E16 D15 C15  J17 J18 K15 J15"
-    set pmod_jc "U12 V12 V10 V11  U14 V14 T13 U13"
+        # Slide switches
+        set sws "V17 V16 W16 W17 W15 V15 W14 W13 V2 T3 T2 R3 W2 U1 T1 R2"
+        set leds "U16 E19 U19 V19 W18 U15 U14 V14 V13 V3 W3 U3 P3 N3 P1 L1"
 
-    # CLK on Pmod JA
-    set pin [lindex $pmod_ja 0]
-    set net2pin(clk) $pin
+        # 100 MHz CLK onboard
+        set pin "W5"
+        set net2pin(clk) $pin
 
-    # DIN on Pmod JB
-    for {set i 0} {$i < $DIN_N} {incr i} {
-        set pin [lindex $pmod_jb $i]
-        set net2pin(din[$i]) $pin
+        # DIN
+        for {set i 0} {$i < $DIN_N} {incr i} {
+            set pin [lindex $sws $i]
+            set net2pin(din[$i]) $pin
+        }
+
+        # DOUT
+        for {set i 0} {$i < $DOUT_N} {incr i} {
+            set pin [lindex $leds $i]
+            set net2pin(dout[$i]) $pin
+       }
+    } else {
+        error "Unsupported config $pincfg"
     }
-
-    # DOUT on Pmod JC
-    for {set i 0} {$i < $DOUT_N} {incr i} {
-        set pin [lindex $pmod_jc $i]
-        set net2pin(dout[$i]) $pin
-   }
 } else {
-    error "Unsupported part $part"
+    error "Pins: unsupported part $part"
 }
 
 # Now actually apply the pin definitions
@@ -338,8 +384,11 @@ if {1} {
             } elseif {$part eq "xc7a35tcsg324-1"} {
                 set node "INT_L_X10Y${y}/SW6BEG0"
                 route_via2 "roi/dout[$i]" "$node"
+            } elseif {$part eq "xc7a35tcpg236-1"} {
+                set node "INT_L_X10Y${y}/SW6BEG0"
+                route_via2 "roi/dout[$i]" "$node"
             } else {
-                error "Unsupported part $part"
+                error "Routing: unsupported part $part"
             }
         # XXX: only care about right ports on Arty
         } else {
@@ -357,6 +406,7 @@ close $fp
 puts "routing design"
 route_design
 
-write_checkpoint -force design.dcp
-write_bitstream -force design.bit
+write_checkpoint -force $outdir/design.dcp
+set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
+write_bitstream -force $outdir/design.bit
 
diff --git a/minitests/roi_harness/top.v b/minitests/roi_harness/top.v
index efe551fe..997231a9 100644
--- a/minitests/roi_harness/top.v
+++ b/minitests/roi_harness/top.v
@@ -1,12 +1,6 @@
 //See README and tcl for more info
 
-`ifndef DIN_N
-`define DIN_N 4
-`endif
-
-`ifndef DOUT_N
-`define DOUT_N 4
-`endif
+`include "defines.v"
 
 module top(input wire clk,
         input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
@@ -18,48 +12,3 @@ module top(input wire clk,
         .din(din), .dout(dout));
 endmodule
 
-module roi(input clk,
-        input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
-    parameter DIN_N = 4;
-    parameter DOUT_N = 4;
-
-    genvar i;
-    generate
-        //CLK
-        (* KEEP, DONT_TOUCH *)
-        reg clk_reg;
-        always @(posedge clk) begin
-            clk_reg <= clk_reg;
-        end
-
-        //DIN
-        for (i = 0; i < DIN_N; i = i+1) begin:ins
-            (* KEEP, DONT_TOUCH *)
-            LUT6 #(
-                .INIT(64'b01)
-            ) lut (
-                .I0(din[i]),
-                .I1(1'b0),
-                .I2(1'b0),
-                .I3(1'b0),
-                .I4(1'b0),
-                .I5(1'b0),
-                .O());
-        end
-
-        //DOUT
-        for (i = 0; i < DOUT_N; i = i+1) begin:outs
-            (* KEEP, DONT_TOUCH *)
-            LUT6 #(
-                .INIT(64'b01)
-            ) lut (
-                .I0(1'b0),
-                .I1(1'b0),
-                .I2(1'b0),
-                .I3(1'b0),
-                .I4(1'b0),
-                .I5(1'b0),
-                .O(dout[i]));
-        end
-    endgenerate
-endmodule
diff --git a/tools/fasm2frame.py b/tools/fasm2frame.py
old mode 100644
new mode 100755
index 622b85cc..c29b9295
--- a/tools/fasm2frame.py
+++ b/tools/fasm2frame.py
@@ -183,6 +183,7 @@ def run(f_in, f_out, sparse=False, debug=False):
             'INT_L': int2dbkey,
             'INT_R': int2dbkey,
             'HCLK_L': int2dbkey,
+            'HCLK_R': int2dbkey,
         }
 
         f = tile2dbkey.get(tilej['type'], None)
diff --git a/tools/segprint2fasm.py b/tools/segprint2fasm.py
old mode 100644
new mode 100755
index 198f795b..4d4e37d5
--- a/tools/segprint2fasm.py
+++ b/tools/segprint2fasm.py
@@ -61,10 +61,11 @@ def tag2fasm(grid, seg, tag):
         'INT_L': intf,
         'INT_R': intf,
         'HCLK_L': intf,
+        'HCLK_R': intf,
     }
     f = tag2asm.get(tile_type, None)
     if f is None:
-        raise Exception("Unhandled segment type %s" % tilej['type'])
+        raise Exception("Unhandled segment type %s" % tile_type)
     return f(seg, tile, tag_post)