mirror of https://github.com/openXC7/prjxray.git
Refactor 041 fuzzer to avoid requiring insight into mux structure.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
5091d0a59e
commit
023cd55bb1
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@ -1,5 +1,5 @@
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export FUZDIR=$(shell pwd)
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PIP_TYPE?=clk_hrow_bot
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PIP_TYPE?=clk_hrow
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PIPLIST_TCL=$(FUZDIR)/clk_hrow_pip_list.tcl
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ifeq (${XRAY_PART}, xc7z010clg400-1)
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@ -7,14 +7,14 @@ ifeq (${XRAY_PART}, xc7z010clg400-1)
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# be documented.
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TODO_RE="[^\.]+\.CLK_HROW_CK_MUX_OUT_[LR][0-9]+\.CLK_HROW_.*[KR_][0-9]+"
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else
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TODO_RE="[^\.]+\.CLK_HROW_CK_MUX_OUT_"
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TODO_RE=".*"
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endif
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MAKETODO_FLAGS=--no-l --pip-type ${PIP_TYPE} --seg-type clk_hrow_bot --re $(TODO_RE)
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MAKETODO_FLAGS=--sides "bot_r,top_r" --pip-type ${PIP_TYPE} --seg-type clk_hrow --re $(TODO_RE)
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N = 50
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# These PIPs all appear to be either a 1 bit solutions.
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SEGMATCH_FLAGS=-c 1
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# These PIPs all appear to be either a 2 bit solutions.
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SEGMATCH_FLAGS=-c 2
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SPECIMENS_DEPS=build/cmt_regions.csv
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A_PIPLIST=clk_hrow_bot_r.txt
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@ -31,27 +31,20 @@ build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
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$(shell find build -name segdata_clk_hrow_top_r.txt) \
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$(shell find build -name segdata_clk_hrow_bot_r.txt)
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build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb piplist
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build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_hrow.rdb \
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--seg-fn-out build/segbits_clk_hrow_rc.db
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# Convert row/column into PIP definition.
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python3 merge_clk_entries.py \
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build/segbits_clk_hrow_rc.db \
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$(XRAY_FUZZERS_DIR)/piplist/build/${PIP_TYPE}/clk_hrow_bot_r.txt \
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build/segbits_clk_hrow.db
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--seg-fn-out build/segbits_clk_hrow.db
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# Keep a copy to track iter progress
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cp build/segbits_clk_hrow.rdb build/$(ITER)/segbits_clk_hrow.rdb
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cp build/segbits_clk_hrow_rc.db build/$(ITER)/segbits_clk_hrow_rc.db
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${XRAY_MASKMERGE} build/mask_clk_hrow.db \
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$(shell find build -name segdata_clk_hrow_top_r.txt) \
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$(shell find build -name segdata_clk_hrow_bot_r.txt)
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# Clobber existing .db to eliminate potential conflicts
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rm -f build/database/${XRAY_DATABASE}/*
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow.db
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@ -1,34 +0,0 @@
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HCLKS = 24
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GCLKS = 32
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SIDE_CLK_INPUTS = 14
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CLK_TABLE_NUM_ROWS = 8
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CLK_TABLE_NUM_COLS = 8
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def get_clk_table():
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clk_table = {}
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for gclk in range(GCLKS):
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gclk_name = 'CLK_HROW_R_CK_GCLK{}'.format(gclk)
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row = gclk % CLK_TABLE_NUM_ROWS
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column = int(gclk / CLK_TABLE_NUM_ROWS)
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clk_table[gclk_name] = (row, column)
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for row in range(8):
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clk_table['CLK_HROW_CK_IN_L{}'.format(row)] = (row, 4)
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for row in range(6):
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clk_table['CLK_HROW_CK_IN_L{}'.format(row + 8)] = (row, 5)
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for row in range(8):
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clk_table['CLK_HROW_CK_IN_R{}'.format(row)] = (row, 6)
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for row in range(6):
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clk_table['CLK_HROW_CK_IN_R{}'.format(row + 8)] = (row, 7)
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# HROW_CK_INT_<X>_<Y>, Y == Y share the same bits, and only X = 0 or X = 1
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# are present on a particular HROW.
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for y in range(2):
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for x in range(2):
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int_clk_name = 'CLK_HROW_CK_INT_{}_{}'.format(x, y)
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clk_table[int_clk_name] = (y + 6, 7)
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return clk_table
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@ -1,17 +1,46 @@
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#!/usr/bin/env python3
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import os
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import os.path
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from prjxray.segmaker import Segmaker
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import clk_table
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import pprint
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def main():
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segmk = Segmaker("design.bits")
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table = clk_table.get_clk_table()
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tiledata = {}
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pipdata = {}
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clk_list = {}
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ignpip = set()
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'clk_hrow', 'clk_hrow_bot_r.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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clk_list[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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clk_list[tile_type].add(src)
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'clk_hrow', 'clk_hrow_top_r.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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clk_list[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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clk_list[tile_type].add(src)
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print("Loading tags from design.txt.")
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active_gclks = {}
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active_clks = {}
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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@ -19,36 +48,46 @@ def main():
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if not tile.startswith('CLK_HROW'):
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continue
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pip_prefix, pip = pip.split(".")
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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rows = set(range(clk_table.CLK_TABLE_NUM_ROWS))
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columns = set(range(clk_table.CLK_TABLE_NUM_COLS))
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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if src in table:
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row, column = table[src]
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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segmk.add_tile_tag(
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tile, '{}.HCLK_ENABLE_ROW{}'.format(dst, row), 1)
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segmk.add_tile_tag(
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tile, '{}.HCLK_ENABLE_COLUMN{}'.format(dst, column), 1)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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rows.remove(row)
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columns.remove(column)
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if pnum == 1 or pdir == 0:
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ignpip.add((src, dst))
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for row in rows:
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segmk.add_tile_tag(
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tile, '{}.HCLK_ENABLE_ROW{}'.format(dst, row), 0)
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active_gclks = {}
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active_clks = {}
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for column in columns:
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segmk.add_tile_tag(
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tile, '{}.HCLK_ENABLE_COLUMN{}'.format(dst, column), 0)
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if tile not in active_clks:
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active_clks[tile] = set()
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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if tile not in active_clks:
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active_clks[tile] = set()
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for src, dst in pips_srcs_dsts["pips"]:
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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active_clks[tile].add(src)
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@ -58,18 +97,26 @@ def main():
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active_gclks[src].add(tile)
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tiles = sorted(active_clks.keys())
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in tiledata[tile]["dsts"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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for tile_type, srcs in clk_list.items():
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for tile, pips_srcs_dsts in tiledata.items():
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for src in srcs:
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if 'GCLK' not in src:
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active = src in active_clks[tile]
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), active)
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else:
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if src not in active_gclks:
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 0)
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elif tile in active_gclks[src]:
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 1)
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for tile in active_clks:
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for src in table:
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if 'GCLK' not in src:
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active = src in active_clks[tile]
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), active)
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else:
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if src not in active_gclks:
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 0)
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elif tile in active_gclks[src]:
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 1)
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segmk.compile()
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segmk.write()
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@ -1,89 +0,0 @@
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import argparse
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import clk_table
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def main():
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parser = argparse.ArgumentParser(
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description="Convert HCLK ROW/COLUMN definitions into HCLK pips.")
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parser.add_argument('in_segbit')
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parser.add_argument('piplist')
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parser.add_argument('out_segbit')
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args = parser.parse_args()
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output_features = []
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hrow_outs = {}
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tile = None
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with open(args.in_segbit) as f:
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for l in f:
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parts = l.strip().split(' ')
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feature = parts[0]
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bits = ' '.join(parts[1:])
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# No post-processing on _ACTIVE bits.
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if feature.endswith('_ACTIVE'):
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output_features.append(l.strip())
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continue
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tile1, dst, src = feature.split('.')
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if tile is None:
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tile = tile1
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else:
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assert tile == tile1
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n = int(src[-1])
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if dst not in hrow_outs:
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hrow_outs[dst] = {
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'rows': {},
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'columns': {},
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}
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if src[-4:-1] == 'ROW':
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hrow_outs[dst]['rows'][n] = bits
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else:
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assert src[-7:-1] == 'COLUMN', src
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hrow_outs[dst]['columns'][n] = bits
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piplists = {}
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with open(args.piplist) as f:
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for l in f:
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tile, dst, src = l.strip().split('.')
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assert tile == 'CLK_HROW_BOT_R', tile
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if dst not in piplists:
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piplists[dst] = []
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piplists[dst].append(src)
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table = clk_table.get_clk_table()
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with open(args.out_segbit, 'w') as f:
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for l in output_features:
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print(l, file=f)
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for dst in sorted(hrow_outs):
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for src in sorted(piplists[dst]):
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if src not in table:
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continue
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row, column = table[src]
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if row not in hrow_outs[dst]['rows']:
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continue
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if column not in hrow_outs[dst]['columns']:
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continue
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print(
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'CLK_HROW.{dst}.{inclk} {row_bits} {column_bits}'.format(
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dst=dst,
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inclk=src,
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row_bits=hrow_outs[dst]['rows'][row],
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column_bits=hrow_outs[dst]['columns'][column],
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),
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file=f)
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if __name__ == "__main__":
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main()
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@ -135,6 +135,8 @@ def check_allowed(mmcm_pll_dir, cmt):
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elif mmcm_pll_dir == 'EVEN':
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x, y = CMT_XY_FUN(cmt)
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return (x & 1) == 0
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elif mmcm_pll_dir == 'NONE':
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return False
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else:
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assert False, mmcm_pll_dir
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@ -162,7 +164,7 @@ module top();
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# sources are allowed. The force of ODD/EVEN/BOTH further biases the
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# clock sources to the left or right column inputs.
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mmcm_pll_only = random.randint(0, 1)
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mmcm_pll_dir = random.choice(('ODD', 'EVEN', 'BOTH'))
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mmcm_pll_dir = random.choice(('ODD', 'EVEN', 'BOTH', 'NONE'))
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if not mmcm_pll_only:
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for _ in range(2):
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@ -279,22 +281,30 @@ module top();
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any_bufhce = False
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for tile_name, sites in gen_bufhce_sites():
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for site in sites:
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wire_name = clock_sources.get_random_source(site_to_cmt[site])
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if wire_name is None:
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continue
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any_bufhce = True
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print(
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"""
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wire I_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I({wire_name})
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.I(I_{site})
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);
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""".format(
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site=site,
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wire_name=wire_name,
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))
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if random.random() > .05:
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wire_name = clock_sources.get_random_source(site_to_cmt[site])
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if wire_name is None:
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continue
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print("""
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assign I_{site} = {wire_name};""".format(
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site=site,
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wire_name=wire_name,
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))
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if not any_bufhce:
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for tile_name, sites in gen_bufhce_sites():
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for site in sites:
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