diff --git a/fuzzers/037-iob-pips/Makefile b/fuzzers/037-iob-pips/Makefile
index 57f3d46b..c150831a 100644
--- a/fuzzers/037-iob-pips/Makefile
+++ b/fuzzers/037-iob-pips/Makefile
@@ -2,15 +2,15 @@ export FUZDIR=$(shell pwd)
 PIP_TYPE?=ioi3
 PIPLIST_TCL=$(FUZDIR)/ioi3_pip_list.tcl
 
-TODO_RE="[LR]IOI3\.(IOI_([IO]LOGIC[01]_CLK(DIV|B)?)|(IOI_OCLK_[01]))\..*"
-EXCLUDE_RE=".*\..*\.(?=IOI_((PHASER)|(OCLK)|(IMUX22_1))).*"
+TODO_RE=".*"
+EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)).*"
 
 MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xr,xl" --exclude-re $(EXCLUDE_RE)
 N = 40
 
 A_PIPLIST=lioi3.txt
 
-SEGMATCH_FLAGS=-c -1 -m 20 -M 50
+SEGMATCH_FLAGS=-c 6 -m 20 -M 50
 SPECIMENS_DEPS=build/cmt_regions.csv
 
 include ../pip_loop.mk
diff --git a/fuzzers/037-iob-pips/generate.py b/fuzzers/037-iob-pips/generate.py
index 4ee3c186..0eeba0b9 100644
--- a/fuzzers/037-iob-pips/generate.py
+++ b/fuzzers/037-iob-pips/generate.py
@@ -69,10 +69,6 @@ def main():
                 tiledata[tile]["srcs"].add(dst)
                 tiledata[tile]["dsts"].add(src)
 
-            if pnum == 1 or pdir == 0:
-                print("Ignoring pip: {}".format(pip), file=log)
-                ignpip.add((src, dst))
-
     for tile, pips_srcs_dsts in tiledata.items():
         tile_type = pips_srcs_dsts["type"]
 
@@ -81,8 +77,6 @@ def main():
         elif tile_type.startswith('RIOI3'):
             tile_type = 'RIOI3'
 
-        pips = pips_srcs_dsts["pips"]
-
         for src, dst in pipdata[tile_type]:
             if (src, dst) in ignpip:
                 pass
@@ -92,9 +86,18 @@ def main():
             elif (src, dst) in tiledata[tile]["pips"]:
                 segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
             elif dst not in tiledata[tile]["dsts"]:
-                segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
+                disable_pip = True
 
-        internal_feedback = False
+                if dst == 'IOI_OCLKM_0' and 'IOI_OCLK_0' in tiledata[tile][
+                        "dsts"]:
+                    disable_pip = False
+
+                if dst == 'IOI_OCLKM_1' and 'IOI_OCLK_1' in tiledata[tile][
+                        "dsts"]:
+                    disable_pip = False
+
+                if disable_pip:
+                    segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
 
     segmk.compile(bitfilter=bitfilter)
     segmk.write()
diff --git a/fuzzers/037-iob-pips/ioi3_pip_list.tcl b/fuzzers/037-iob-pips/ioi3_pip_list.tcl
index d7c940af..f592f9f6 100644
--- a/fuzzers/037-iob-pips/ioi3_pip_list.tcl
+++ b/fuzzers/037-iob-pips/ioi3_pip_list.tcl
@@ -2,7 +2,6 @@ proc print_tile_pips {tile_type filename} {
     set fp [open $filename w]
     set pips [dict create]
     foreach tile [get_tiles -filter "TYPE == $tile_type"] {
-        puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
         foreach pip [lsort [get_pips -of_objects  $tile]] {
             set src [get_wires -uphill -of_objects $pip]
             set dst [get_wires -downhill -of_objects $pip]
@@ -19,7 +18,10 @@ proc print_tile_pips {tile_type filename} {
                 continue
             }
 
-            if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
+            set src_wire [regsub {.*/} $src ""]
+            set src_match [regexp {IOI_OCLKM?_[01]} $src_wire]
+
+            if { [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1 || $src_match } {
                 set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
                 if ![dict exists $pips $pip_string] {
                     puts $fp $pip_string
diff --git a/fuzzers/037-iob-pips/top.py b/fuzzers/037-iob-pips/top.py
index e6e4e3f0..3346b425 100644
--- a/fuzzers/037-iob-pips/top.py
+++ b/fuzzers/037-iob-pips/top.py
@@ -259,6 +259,8 @@ def run():
                 .INTERFACE_TYPE({INTERFACE_TYPE}),
                 .IS_CLK_INVERTED({IS_CLK_INVERTED}),
                 .IS_CLKB_INVERTED({IS_CLKB_INVERTED}),
+                .IS_OCLK_INVERTED({IS_OCLK_INVERTED}),
+                .IS_OCLKB_INVERTED({IS_OCLKB_INVERTED}),
                 .INIT_Q1({INIT_Q1}),
                 .INIT_Q2({INIT_Q2}),
                 .INIT_Q3({INIT_Q3}),
@@ -275,6 +277,8 @@ def run():
                         INTERFACE_TYPE=verilog.quote(INTERFACE_TYPE),
                         IS_CLK_INVERTED=random.randint(0, 1),
                         IS_CLKB_INVERTED=random.randint(0, 1),
+                        IS_OCLK_INVERTED=random.randint(0, 1),
+                        IS_OCLKB_INVERTED=random.randint(0, 1),
                         INIT_Q1=random.randint(0, 1),
                         INIT_Q2=random.randint(0, 1),
                         INIT_Q3=random.randint(0, 1),
@@ -324,10 +328,12 @@ def run():
                     """
             (* KEEP, DONT_TOUCH, LOC = "{site}" *)
             OSERDESE2 #(
+                .IS_CLK_INVERTED({IS_CLK_INVERTED}),
                 .DATA_RATE_OQ("SDR"),
                 .DATA_RATE_TQ("SDR")
             ) oserdes_{site} (
                 {ports});""".format(
+                        IS_CLK_INVERTED=random.randint(0, 1),
                         site=ologic_site,
                         ports=',\n'.join(ports),
                     ))