mirror of https://github.com/openXC7/prjxray.git
dbfixup: quick hacks to make 050 happy
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
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@ -119,6 +119,11 @@ def add_zero_bits(fn_in, fn_out, zero_db, clb_int=False, verbose=False):
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line = line.strip()
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line = line.strip()
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if line == llast:
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if line == llast:
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continue
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continue
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# FIXME: quick workaround
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# was in mergedb.sh
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# if re.match(r'.*<m.*>.*', line):
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if re.match(r'.*<.*>.*', line):
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continue
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tag, bits, mode = util.parse_db_line(line)
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tag, bits, mode = util.parse_db_line(line)
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assert mode not in (
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assert mode not in (
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@ -127,20 +132,20 @@ def add_zero_bits(fn_in, fn_out, zero_db, clb_int=False, verbose=False):
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if mode == "always":
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if mode == "always":
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new_line = line
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new_line = line
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elif mode == "<0 candidates>":
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else:
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if mode:
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assert mode == "<0 candidates>", line
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bits = set(bits)
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"""
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"""
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This appears to be a large range of one hot interconnect bits
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This appears to be a large range of one hot interconnect bits
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They are immediately before the first CLB real bits
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They are immediately before the first CLB real bits
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"""
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"""
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if clb_int:
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if clb_int:
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zero_range(bits, 22, 25)
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zero_range(bits, 22, 25)
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bits = set(bits)
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zero_groups(
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zero_groups(
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tag, bits, zero_db, strict=not clb_int, verbose=verbose)
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tag, bits, zero_db, strict=not clb_int, verbose=verbose)
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new_line = " ".join([tag] + sorted(bits))
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new_line = " ".join([tag] + sorted(bits))
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else:
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assert 0, line
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if new_line != line:
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if new_line != line:
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changes += 1
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changes += 1
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