diff --git a/utils/dbfixup.py b/utils/dbfixup.py
index 094629aa..266a2fd1 100755
--- a/utils/dbfixup.py
+++ b/utils/dbfixup.py
@@ -119,6 +119,11 @@ def add_zero_bits(fn_in, fn_out, zero_db, clb_int=False, verbose=False):
             line = line.strip()
             if line == llast:
                 continue
+            # FIXME: quick workaround
+            # was in mergedb.sh
+            # if re.match(r'.*<m.*>.*', line):
+            if re.match(r'.*<.*>.*', line):
+                continue
 
             tag, bits, mode = util.parse_db_line(line)
             assert mode not in (
@@ -127,20 +132,20 @@ def add_zero_bits(fn_in, fn_out, zero_db, clb_int=False, verbose=False):
 
             if mode == "always":
                 new_line = line
-            elif mode == "<0 candidates>":
+            else:
+                if mode:
+                    assert mode == "<0 candidates>", line
+                bits = set(bits)
                 """
                 This appears to be a large range of one hot interconnect bits
                 They are immediately before the first CLB real bits
                 """
                 if clb_int:
                     zero_range(bits, 22, 25)
-                bits = set(bits)
                 zero_groups(
                     tag, bits, zero_db, strict=not clb_int, verbose=verbose)
 
                 new_line = " ".join([tag] + sorted(bits))
-            else:
-                assert 0, line
 
             if new_line != line:
                 changes += 1