ffprim: merge in latch research

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

experiments/ffprim/generate.py

@@ -1,5 +1,7 @@
 #!/usr/bin/env python3
 
+from prims import *
+
 import sys, re
 
 sys.path.append("../../../utils/")
@@ -7,34 +9,14 @@ from segmaker import segmaker
 
 segmk = segmaker("design.bits")
 
-ffprims = (
+def ones(l):
-        'FD',
+    #return l + [x + '_1' for x in l]
-        'FD_1',
+    #return sorted(l + [x + '_1' for x in l])
-        'FDC',
+    ret = []
-        'FDC_1',
+    for x in l:
-        'FDCE',
+        ret.append(x)
-        'FDCE_1',
+        ret.append(x + '_1')
-        'FDE',
+    return ret
-        'FDE_1',
-        'FDP',
-        'FDP_1',
-        'FDPE',
-        'FDPE_1',
-        'FDR',
-        'FDR_1',
-        'FDRE',
-        'FDRE_1',
-        'FDS',
-        'FDS_1',
-        'FDSE',
-        'FDSE_1',
-        )
-ffprims = (
-        'FDRE',
-        'FDSE',
-        'FDCE',
-        'FDPE',
-        )
 
 print("Loading tags from design.txt")
 with open("design.txt", "r") as f:
@@ -55,11 +37,12 @@ with open("design.txt", "r") as f:
         site, ff_name = site_ff_name.split('/')
         ff_type = line[5]
         used = int(line[6])
-        ref_name = None
+        cel_prim = None
         cel_name = None
         if used:
             cel_name = line[7]
-            ref_name = line[8]
+            # ex: FDCE
+            cel_prim = line[8]
             # 1'b1
             # cinv = int(line[9][-1])
             cinv = int(line[9])
@@ -68,30 +51,63 @@ with open("design.txt", "r") as f:
         # Reduced test for now
         #if ff_name != 'AFF':
         #    continue
+        
+        is5 = '5' in ff_name
 
         #segmk.addtag(site, "FF_USED", used)
-        if 0:
+        if 1:
             # If unused mark all primitives as not present
             # Otherwise mark the primitive we are using
-            for ffprim in ffprims:
+            if used:
-                if not used:
+                segmk.addtag(site, "%s.%s" % (ff_name, cel_prim), 1)
-                    segmk.addtag(site, "FF_%s" % ffprim, 0)
+            else:
-                elif ref_name == ffprim:
+                for ffprim in ffprims:
-                    segmk.addtag(site, "FF_%s" % ffprim, 1)
+                    # FF's don't do 5's
+                    if isff(ffprim) or (isl(ffprim) and not is5):
+                        segmk.addtag(site, "%s.%s" % (ff_name, ffprim), 0)
 
         # Theory:
         # FDPE represents none of the FF specific bits used
-        # FDRE has none of the bits used
+        # FDRE has all of the bits used
-        if 1:
+        if 0:
             # If unused mark all primitives as not present
             # Otherwise mark the primitive we are using
             # Should yield 3 bits
             if used:
-                if ref_name == 'FDPE':
+                if cel_prim == 'FDPE':
                     segmk.addtag(site, "%s.PRIM" % ff_name, 0)
-                if ref_name == 'FDRE':
+                if cel_prim == 'FDRE':
                     segmk.addtag(site, "%s.PRIM" % ff_name, 1)
 
+        # FF specific test
+        # Theory: FDSE and FDCE are the most and least encoded FF's
+        if 1:
+            # If unused mark all primitives as not present
+            # Otherwise mark the primitive we are using
+            # Should yield 3 bits
+            if used and isff(cel_prim):
+                # PRIM1 is now FFSYNC
+                #segmk.addtag(site, "%s.PRIM1" % ff_name,
+                #    cel_prim in ('FDSE', 'FDRE'))
+                segmk.addtag(site, "%s.PRIM2" % ff_name,
+                    cel_prim in ('FDCE', 'FDRE'))
+        
+        # Theory: there are some common enable bits
+        '''
+                00_48   30_32   30_12   31_03
+        FDPE
+        FDSE    X
+        FDRE    X               X       X
+        FDCE                    X       X
+        LDCE            X       X       X
+        LDPE            X
+
+        00_48 is shared between all X0 FFs
+        '''
+        if 1 and used:
+            segmk.addtag(site, "FFSYNC",
+                    cel_prim in ('FDSE', 'FDRE'))
+
 segmk.compile()
 segmk.write()
 

experiments/ffprim/generate.tcl

@@ -48,7 +48,9 @@ foreach ff $ffs {
         set ref_name [get_property REF_NAME $ffc]
         #set cinv [get_property IS_C_INVERTED $ffc]
 
-        set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C}]
+        # FF have clock pin
+        # Latches have gate pin
+        set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}]
         set cinv [get_property IS_INVERTED $cpin]
         set usedstr "$cell_bel $ref_name $cinv"
     }

experiments/ffprim/prims.py

@@ -0,0 +1,61 @@
+def ones(l):
+    #return l + [x + '_1' for x in l]
+    #return sorted(l + [x + '_1' for x in l])
+    ret = []
+    for x in l:
+        ret.append(x)
+        ret.append(x + '_1')
+    return ret
+
+ffprims_fall = ones([
+        'FD',
+        'FDC',
+        'FDCE',
+        'FDE',
+        'FDP',
+        'FDPE',
+        'FDR',
+        'FDRE',
+        'FDS',
+        'FDSE',
+        ])
+ffprims_f = [
+        'FDRE',
+        'FDSE',
+        'FDCE',
+        'FDPE',
+        ]
+ffprims_lall = ones([
+        'LDC',
+        'LDCE',
+        'LDE',
+        'LDPE',
+        'LDP',
+        ])
+ffprims_l = [
+        'LDCE',
+        'LDPE',
+        ]
+ffprims = ffprims_f + ffprims_l
+
+def isff(prim):
+    return prim.startswith("FD")
+
+def isl(prim):
+    return prim.startswith("LD")
+
+ff_bels_5 = [
+        'A5FF',
+        'B5FF',
+        'C5FF',
+        'D5FF',
+        ]
+ff_bels_ffl = [
+        'AFF',
+        'BFF',
+        'CFF',
+        'DFF',
+        ]
+ff_bels = ff_bels_ffl + ff_bels_5
+#ff_bels = ff_bels_ffl
+

experiments/ffprim/top.py

@@ -1,3 +1,5 @@
+from prims import *
+
 import random
 
 random.seed(0)
@@ -21,44 +23,6 @@ def gen_slices():
 
 DIN_N = CLBN * 4
 DOUT_N = CLBN * 1
-ffprims = (
-        'FD',
-        'FD_1',
-        'FDC',
-        'FDC_1',
-        'FDCE',
-        'FDCE_1',
-        'FDE',
-        'FDE_1',
-        'FDP',
-        'FDP_1',
-        'FDPE',
-        'FDPE_1',
-        'FDR',
-        'FDR_1',
-        'FDRE',
-        'FDRE_1',
-        'FDS',
-        'FDS_1',
-        'FDSE',
-        'FDSE_1',
-        )
-ffprims = (
-        'FDRE',
-        'FDSE',
-        'FDCE',
-        'FDPE',
-)
-ff_bels = (
-        'AFF',
-        'A5FF',
-        'BFF',
-        'B5FF',
-        'CFF',
-        'C5FF',
-        'DFF',
-        'D5FF',
-        )
 
 print('''
 module top(input clk, stb, di, output do);
@@ -97,7 +61,11 @@ for i in range(CLBN):
     # clb_FD clb_FD (.clk(clk), .din(din[  0 +: 4]), .dout(dout[  0]));
     # clb_FD_1 clb_FD_1 (.clk(clk), .din(din[  4 +: 4]), .dout(dout[  1]));
     loc = next(slices)
-    bel = random.choice(ff_bels)
+    # Latch can't go in 5s
+    if isff(ffprim):
+        bel = random.choice(ff_bels)
+    else:
+        bel = random.choice(ff_bels_ffl)
     #bel = "AFF"
     print('    clb_%s' % ffprim)
     print('            #(.LOC("%s"), .BEL("%s"))' % (loc, bel))
@@ -354,5 +322,129 @@ module clb_FDSE_1 (input clk, input [3:0] din, output dout);
 		.D(din[2])
 	);
 	endmodule
+
+//********************************************************************************
+
+module clb_LDC (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y120";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDC ff (
+		.G(~clk),
+		.Q(dout),
+		.D(din[0]),
+		.CLR(din[1])
+	);
+	endmodule
+module clb_LDC_1 (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y121";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDC_1 ff (
+		.G(~clk),
+		.Q(dout),
+		.D(din[0]),
+		.CLR(din[1])
+	);
+	endmodule
+
+module clb_LDCE (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y122";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDCE ff (
+		.G(~clk),
+		//NOTE: diagram shows two outputs. Error?
+		.Q(dout),
+		.D(din[0]),
+		.GE(din[1]),
+		.CLR(din[2])
+	);
+	endmodule
+module clb_LDCE_1 (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y123";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDCE_1 ff (
+		.G(~clk),
+		//NOTE: diagram shows two outputs. Error?
+		.Q(dout),
+		.D(din[0]),
+		.GE(din[1]),
+		.CLR(din[2])
+	);
+	endmodule
+
+module clb_LDE (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y124";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDE ff (
+		.G(~clk),
+		.Q(dout),
+		.D(din[0]),
+		.GE(din[1])
+	);
+	endmodule
+module clb_LDE_1 (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y125";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDE_1 ff (
+		.G(~clk),
+		.Q(dout),
+		.D(din[0]),
+		.GE(din[1])
+	);
+	endmodule
+
+module clb_LDP (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y126";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDP ff (
+		.G(~clk),
+		.Q(dout),
+		.D(din[0]),
+		.PRE(din[1])
+	);
+	endmodule
+module clb_LDP_1 (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y127";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDP_1 ff (
+		.G(~clk),
+		.Q(dout),
+		.D(din[0]),
+		.PRE(din[1])
+	);
+	endmodule
+
+module clb_LDPE (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y128";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDPE ff (
+		.G(~clk),
+		.Q(dout),
+		.PRE(din[0]),
+		.D(din[1]),
+		.GE(din[2])
+	);
+	endmodule
+module clb_LDPE_1 (input clk, input [3:0] din, output dout);
+    parameter LOC="SLICE_X16Y129";
+    parameter BEL="AFF";
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LDPE_1 ff (
+		.G(~clk),
+		.Q(dout),
+		.PRE(din[0]),
+		.D(din[1]),
+		.GE(din[2])
+	);
+	endmodule
+
 ''')