mirror of https://github.com/openXC7/prjxray.git
ffcfg: add latch primitives
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
6eb44b0c33
commit
c5f02a0075
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@ -1,9 +1,15 @@
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//https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/7series_scm.pdf
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//Places one of every FF primitive
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/*
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LDC => LDCE
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LDE => LDCE
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LDP => LDPE
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*/
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 80;
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localparam integer DOUT_N = 20;
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localparam integer DIN_N = 120;
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localparam integer DOUT_N = 30;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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@ -29,7 +35,7 @@ module top(input clk, stb, di, output do);
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);
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endmodule
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module roi(input clk, input [79:0] din, output [19:0] dout);
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module roi(input clk, input [119:0] din, output [29:0] dout);
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/*
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clbs = (
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'FD',
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@ -52,10 +58,22 @@ module roi(input clk, input [79:0] din, output [19:0] dout);
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'FDS_1',
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'FDSE',
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'FDSE_1',
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'LDC',
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'LDC_1',
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'LDCE',
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'LDCE_1',
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'LDE',
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'LDE_1',
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'LDPE',
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'LDPE_1',
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'LDP',
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'LDP_1',
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)
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for i, clb in enumerate(clbs):
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print 'clb_%s clb_%s (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d ]));' % (clb, clb, i * 4, i * 1)
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*/
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//FD
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clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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clb_FDC clb_FDC (.clk(clk), .din(din[ 8 +: 4]), .dout(dout[ 2]));
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@ -76,6 +94,17 @@ module roi(input clk, input [79:0] din, output [19:0] dout);
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clb_FDS_1 clb_FDS_1 (.clk(clk), .din(din[ 68 +: 4]), .dout(dout[ 17]));
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clb_FDSE clb_FDSE (.clk(clk), .din(din[ 72 +: 4]), .dout(dout[ 18]));
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clb_FDSE_1 clb_FDSE_1 (.clk(clk), .din(din[ 76 +: 4]), .dout(dout[ 19]));
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//LD
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clb_LDC clb_LDC (.clk(clk), .din(din[ 80 +: 4]), .dout(dout[ 20 ]));
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clb_LDC_1 clb_LDC_1 (.clk(clk), .din(din[ 84 +: 4]), .dout(dout[ 21 ]));
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clb_LDCE clb_LDCE (.clk(clk), .din(din[ 88 +: 4]), .dout(dout[ 22 ]));
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clb_LDCE_1 clb_LDCE_1 (.clk(clk), .din(din[ 92 +: 4]), .dout(dout[ 23 ]));
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clb_LDE clb_LDE (.clk(clk), .din(din[ 96 +: 4]), .dout(dout[ 24 ]));
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clb_LDE_1 clb_LDE_1 (.clk(clk), .din(din[ 100 +: 4]), .dout(dout[ 25 ]));
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clb_LDPE clb_LDPE (.clk(clk), .din(din[ 104 +: 4]), .dout(dout[ 26 ]));
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clb_LDPE_1 clb_LDPE_1 (.clk(clk), .din(din[ 108 +: 4]), .dout(dout[ 27 ]));
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clb_LDP clb_LDP (.clk(clk), .din(din[ 112 +: 4]), .dout(dout[ 28 ]));
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clb_LDP_1 clb_LDP_1 (.clk(clk), .din(din[ 116 +: 4]), .dout(dout[ 29 ]));
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endmodule
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// ---------------------------------------------------------------------
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@ -88,7 +117,6 @@ module clb_FD (input clk, input [3:0] din, output dout);
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.D(din[0])
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);
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endmodule
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module clb_FD_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y101", BEL="AFF" *)
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FD_1 ff (
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@ -107,7 +135,6 @@ module clb_FDC (input clk, input [3:0] din, output dout);
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.D(din[1])
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);
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endmodule
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module clb_FDC_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y103", BEL="AFF" *)
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FDC_1 ff (
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@ -128,7 +155,6 @@ module clb_FDCE (input clk, input [3:0] din, output dout);
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.D(din[2])
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);
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endmodule
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module clb_FDCE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y105", BEL="AFF" *)
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FDCE_1 ff (
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@ -149,7 +175,6 @@ module clb_FDE (input clk, input [3:0] din, output dout);
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.CE(din[1])
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);
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endmodule
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module clb_FDE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y107", BEL="AFF" *)
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FDE_1 ff (
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@ -169,7 +194,6 @@ module clb_FDP (input clk, input [3:0] din, output dout);
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.PRE(din[1])
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);
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endmodule
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module clb_FDP_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y109", BEL="AFF" *)
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FDP_1 ff (
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@ -190,7 +214,6 @@ module clb_FDPE (input clk, input [3:0] din, output dout);
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.D(din[2])
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);
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endmodule
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module clb_FDPE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y111", BEL="AFF" *)
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FDPE_1 ff (
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@ -211,7 +234,6 @@ module clb_FDR (input clk, input [3:0] din, output dout);
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.R(din[1])
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);
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endmodule
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module clb_FDR_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y113", BEL="AFF" *)
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FDR_1 ff (
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@ -232,7 +254,6 @@ module clb_FDRE (input clk, input [3:0] din, output dout);
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.D(din[2])
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);
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endmodule
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module clb_FDRE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y115", BEL="AFF" *)
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FDRE_1 ff (
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@ -253,7 +274,6 @@ module clb_FDS (input clk, input [3:0] din, output dout);
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.D(din[1])
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);
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endmodule
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module clb_FDS_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y117", BEL="AFF" *)
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FDS_1 ff (
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@ -274,7 +294,6 @@ module clb_FDSE (input clk, input [3:0] din, output dout);
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.D(din[2])
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);
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endmodule
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module clb_FDSE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y119", BEL="AFF" *)
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FDSE_1 ff (
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@ -286,3 +305,126 @@ module clb_FDSE_1 (input clk, input [3:0] din, output dout);
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);
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endmodule
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//********************************************************************************
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module clb_LDC (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y120";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDC ff (
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.G(clk),
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.Q(dout),
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.D(din[0]),
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.CLR(din[1])
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);
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endmodule
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module clb_LDC_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y121";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDC_1 ff (
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.G(clk),
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.Q(dout),
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.D(din[0]),
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.CLR(din[1])
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);
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endmodule
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module clb_LDCE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y122";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDCE ff (
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.G(clk),
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//NOTE: diagram shows two outputs. Error?
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.Q(dout),
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.D(din[0]),
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.GE(din[1]),
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.CLR(din[2])
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);
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endmodule
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module clb_LDCE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y123";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDCE_1 ff (
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.G(clk),
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//NOTE: diagram shows two outputs. Error?
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.Q(dout),
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.D(din[0]),
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.GE(din[1]),
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.CLR(din[2])
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);
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endmodule
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module clb_LDE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y124";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDE ff (
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.G(clk),
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.Q(dout),
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.D(din[0]),
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.GE(din[1])
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);
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endmodule
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module clb_LDE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y125";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDE_1 ff (
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.G(clk),
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.Q(dout),
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.D(din[0]),
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.GE(din[1])
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);
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endmodule
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module clb_LDP (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y126";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDP ff (
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.G(clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_LDP_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y127";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDP_1 ff (
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.G(clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_LDPE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y128";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDPE ff (
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.G(clk),
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.Q(dout),
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.PRE(din[0]),
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.D(din[1]),
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.GE(din[2])
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);
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endmodule
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module clb_LDPE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y129";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDPE_1 ff (
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.G(clk),
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.Q(dout),
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.PRE(din[0]),
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.D(din[1]),
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.GE(din[2])
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);
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endmodule
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