mirror of https://github.com/openXC7/prjxray.git
ffprim: merge in latch research
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
c5f02a0075
commit
be3d7ec8c7
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@ -1,5 +1,7 @@
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#!/usr/bin/env python3
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from prims import *
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import sys, re
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sys.path.append("../../../utils/")
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@ -7,34 +9,14 @@ from segmaker import segmaker
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segmk = segmaker("design.bits")
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ffprims = (
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'FD',
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'FD_1',
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'FDC',
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'FDC_1',
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'FDCE',
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'FDCE_1',
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'FDE',
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'FDE_1',
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'FDP',
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'FDP_1',
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'FDPE',
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'FDPE_1',
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'FDR',
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'FDR_1',
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'FDRE',
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'FDRE_1',
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'FDS',
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'FDS_1',
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'FDSE',
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'FDSE_1',
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)
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ffprims = (
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'FDRE',
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'FDSE',
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'FDCE',
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'FDPE',
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)
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def ones(l):
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#return l + [x + '_1' for x in l]
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#return sorted(l + [x + '_1' for x in l])
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ret = []
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for x in l:
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ret.append(x)
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ret.append(x + '_1')
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return ret
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print("Loading tags from design.txt")
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with open("design.txt", "r") as f:
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@ -55,11 +37,12 @@ with open("design.txt", "r") as f:
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site, ff_name = site_ff_name.split('/')
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ff_type = line[5]
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used = int(line[6])
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ref_name = None
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cel_prim = None
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cel_name = None
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if used:
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cel_name = line[7]
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ref_name = line[8]
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# ex: FDCE
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cel_prim = line[8]
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# 1'b1
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# cinv = int(line[9][-1])
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cinv = int(line[9])
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@ -68,30 +51,63 @@ with open("design.txt", "r") as f:
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# Reduced test for now
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#if ff_name != 'AFF':
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# continue
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is5 = '5' in ff_name
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#segmk.addtag(site, "FF_USED", used)
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if 0:
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if 1:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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for ffprim in ffprims:
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if not used:
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segmk.addtag(site, "FF_%s" % ffprim, 0)
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elif ref_name == ffprim:
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segmk.addtag(site, "FF_%s" % ffprim, 1)
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if used:
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segmk.addtag(site, "%s.%s" % (ff_name, cel_prim), 1)
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else:
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for ffprim in ffprims:
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# FF's don't do 5's
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if isff(ffprim) or (isl(ffprim) and not is5):
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segmk.addtag(site, "%s.%s" % (ff_name, ffprim), 0)
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# Theory:
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# FDPE represents none of the FF specific bits used
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# FDRE has none of the bits used
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if 1:
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# FDRE has all of the bits used
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if 0:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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# Should yield 3 bits
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if used:
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if ref_name == 'FDPE':
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if cel_prim == 'FDPE':
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segmk.addtag(site, "%s.PRIM" % ff_name, 0)
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if ref_name == 'FDRE':
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if cel_prim == 'FDRE':
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segmk.addtag(site, "%s.PRIM" % ff_name, 1)
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# FF specific test
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# Theory: FDSE and FDCE are the most and least encoded FF's
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if 1:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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# Should yield 3 bits
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if used and isff(cel_prim):
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# PRIM1 is now FFSYNC
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#segmk.addtag(site, "%s.PRIM1" % ff_name,
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# cel_prim in ('FDSE', 'FDRE'))
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segmk.addtag(site, "%s.PRIM2" % ff_name,
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cel_prim in ('FDCE', 'FDRE'))
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# Theory: there are some common enable bits
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'''
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00_48 30_32 30_12 31_03
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FDPE
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FDSE X
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FDRE X X X
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FDCE X X
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LDCE X X X
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LDPE X
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00_48 is shared between all X0 FFs
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'''
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if 1 and used:
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segmk.addtag(site, "FFSYNC",
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cel_prim in ('FDSE', 'FDRE'))
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segmk.compile()
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segmk.write()
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@ -48,7 +48,9 @@ foreach ff $ffs {
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set ref_name [get_property REF_NAME $ffc]
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#set cinv [get_property IS_C_INVERTED $ffc]
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set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C}]
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# FF have clock pin
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# Latches have gate pin
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set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}]
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set cinv [get_property IS_INVERTED $cpin]
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set usedstr "$cell_bel $ref_name $cinv"
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}
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@ -0,0 +1,61 @@
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def ones(l):
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#return l + [x + '_1' for x in l]
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#return sorted(l + [x + '_1' for x in l])
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ret = []
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for x in l:
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ret.append(x)
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ret.append(x + '_1')
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return ret
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ffprims_fall = ones([
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'FD',
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'FDC',
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'FDCE',
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'FDE',
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'FDP',
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'FDPE',
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'FDR',
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'FDRE',
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'FDS',
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'FDSE',
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])
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ffprims_f = [
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'FDRE',
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'FDSE',
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'FDCE',
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'FDPE',
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]
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ffprims_lall = ones([
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'LDC',
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'LDCE',
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'LDE',
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'LDPE',
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'LDP',
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])
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ffprims_l = [
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'LDCE',
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'LDPE',
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]
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ffprims = ffprims_f + ffprims_l
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def isff(prim):
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return prim.startswith("FD")
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def isl(prim):
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return prim.startswith("LD")
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ff_bels_5 = [
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'A5FF',
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'B5FF',
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'C5FF',
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'D5FF',
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]
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ff_bels_ffl = [
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'AFF',
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'BFF',
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'CFF',
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'DFF',
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]
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ff_bels = ff_bels_ffl + ff_bels_5
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#ff_bels = ff_bels_ffl
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@ -1,3 +1,5 @@
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from prims import *
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import random
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random.seed(0)
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@ -21,44 +23,6 @@ def gen_slices():
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DIN_N = CLBN * 4
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DOUT_N = CLBN * 1
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ffprims = (
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'FD',
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'FD_1',
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'FDC',
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'FDC_1',
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'FDCE',
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'FDCE_1',
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'FDE',
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'FDE_1',
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'FDP',
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'FDP_1',
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'FDPE',
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'FDPE_1',
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'FDR',
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'FDR_1',
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'FDRE',
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'FDRE_1',
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'FDS',
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'FDS_1',
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'FDSE',
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'FDSE_1',
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)
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ffprims = (
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'FDRE',
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'FDSE',
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'FDCE',
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'FDPE',
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)
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ff_bels = (
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'AFF',
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'A5FF',
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'BFF',
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'B5FF',
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'CFF',
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'C5FF',
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'DFF',
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'D5FF',
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)
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print('''
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module top(input clk, stb, di, output do);
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@ -97,7 +61,11 @@ for i in range(CLBN):
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# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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loc = next(slices)
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bel = random.choice(ff_bels)
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# Latch can't go in 5s
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if isff(ffprim):
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bel = random.choice(ff_bels)
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else:
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bel = random.choice(ff_bels_ffl)
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#bel = "AFF"
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print(' clb_%s' % ffprim)
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print(' #(.LOC("%s"), .BEL("%s"))' % (loc, bel))
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@ -354,5 +322,129 @@ module clb_FDSE_1 (input clk, input [3:0] din, output dout);
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.D(din[2])
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);
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endmodule
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//********************************************************************************
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module clb_LDC (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y120";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDC ff (
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.G(~clk),
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.Q(dout),
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.D(din[0]),
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.CLR(din[1])
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);
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endmodule
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module clb_LDC_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y121";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDC_1 ff (
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.G(~clk),
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.Q(dout),
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.D(din[0]),
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.CLR(din[1])
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);
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endmodule
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module clb_LDCE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y122";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDCE ff (
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.G(~clk),
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//NOTE: diagram shows two outputs. Error?
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.Q(dout),
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.D(din[0]),
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.GE(din[1]),
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.CLR(din[2])
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);
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endmodule
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module clb_LDCE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y123";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDCE_1 ff (
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.G(~clk),
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//NOTE: diagram shows two outputs. Error?
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.Q(dout),
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.D(din[0]),
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.GE(din[1]),
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.CLR(din[2])
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);
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endmodule
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module clb_LDE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y124";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDE ff (
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.G(~clk),
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.Q(dout),
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.D(din[0]),
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.GE(din[1])
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);
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endmodule
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module clb_LDE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y125";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDE_1 ff (
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.G(~clk),
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.Q(dout),
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.D(din[0]),
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.GE(din[1])
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);
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endmodule
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module clb_LDP (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y126";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDP ff (
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.G(~clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_LDP_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y127";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDP_1 ff (
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.G(~clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_LDPE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y128";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDPE ff (
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.G(~clk),
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.Q(dout),
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.PRE(din[0]),
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.D(din[1]),
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.GE(din[2])
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);
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endmodule
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module clb_LDPE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y129";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LDPE_1 ff (
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.G(~clk),
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.Q(dout),
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.PRE(din[0]),
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.D(din[1]),
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.GE(din[2])
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);
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endmodule
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''')
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