mirror of https://github.com/openXC7/prjxray.git
Delete abandoned experiment clb_lut5
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
250050024f
commit
bd8a5d8377
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/specimen_*/
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/*.segbits
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N := 3
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits
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.PHONY: database pushdb clean
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@ -1,11 +0,0 @@
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Purpose:
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Understand LUT5 vs LUT6 configuration
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Algorithm:
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Generate a design with LUT6's and LUT6_2's (dual LUT5)
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Compare bitstream differences
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Outcome:
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Discovered an additional bit set when LUT6_2 is used
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@ -1,44 +0,0 @@
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#!/usr/bin/env python3
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import sys, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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print("Loading tags from design.txt")
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with open("design.txt", "r") as f:
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for line in f:
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'''
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puts $fp "$type $tile $grid_x $grid_y $lut $lut_type"
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CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X13Y112/B5LUT LUT5
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CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X13Y112/A6LUT LUT6
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CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X12Y112/C6LUT LUT_OR_MEM6
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CLBLM_L CLBLM_L_X10Y145 30 5 SLICE_X12Y145/D5LUT LUT_OR_MEM5
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updated
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CLBLM_L CLBLM_L_X10Y149 30 1 SLICE_X12Y149/C6LUT LUT_OR_MEM6 SLICEM.C6LUT
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'''
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line = line.split()
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tile_type = line[0]
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tile_name = line[1]
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grid_x = line[2]
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grid_y = line[3]
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# Other code uses BEL name
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site_lut_name = line[4]
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site, lut_name = site_lut_name.split('/')
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lut_type = line[5]
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# SLICEL.A6LUT
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cell_bel = line[6]
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slicelm = cell_bel.split('.')[0]
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which = lut_name[0]
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is_lut5 = lut_type in ('LUT5', 'LUT_OR_MEM5')
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site_mod = site + '.' + slicelm
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site_mod = site
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segmk.addtag(site, slicelm + '.' + "%cLUT5" % which, is_lut5)
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segmk.compile()
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segmk.write()
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@ -1,14 +0,0 @@
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#!/bin/bash
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source ${XRAY_GENHEADER}
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echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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vivado -mode batch -source ../generate.tcl
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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@ -1,64 +0,0 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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# Get all 6LUT and 5LUT in pblock
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# A6LUT, B6LUT, A5LUT, etc
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */*LUT]
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set grid_min_x -1
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set grid_max_x -1
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set grid_min_y -1
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set grid_max_y -1
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
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if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
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if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
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if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
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}
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set fp [open "design.txt" w]
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foreach lut $luts {
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if [get_property IS_USED $lut] {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set type [get_property TYPE $tile]
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set lut_type [get_property TYPE $lut]
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set lutc [get_cells -of_objects $lut]
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set cell_bel [get_property BEL $lutc]
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puts $fp "$type $tile $grid_x $grid_y $lut $lut_type $cell_bel"
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}
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}
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close $fp
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@ -1,112 +0,0 @@
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`include "setseed.vh"
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`define N 1000
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 6;
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localparam integer DOUT_N = `N;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [5:0] din, output [`N-1:0] dout);
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function [31:0] xorshift32(input [31:0] v);
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begin
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xorshift32 = v;
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xorshift32 = xorshift32 ^ (xorshift32 << 13);
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xorshift32 = xorshift32 ^ (xorshift32 >> 17);
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xorshift32 = xorshift32 ^ (xorshift32 << 5);
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end
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endfunction
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function [31:0] hash32(input [31:0] v);
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begin
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hash32 = v ^ `SEED;
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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end
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endfunction
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function [63:0] hash64(input [31:0] v);
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begin
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hash64[63:32] = hash32(v);
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hash64[31: 0] = hash32(~v);
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end
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endfunction
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genvar i;
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generate
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for (i = 0; i < `N; i = i+1) begin:is
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/*
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wire o5;
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wire o6;
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assign dout[i] = o5 & o6;
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LUT5 #(
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.INIT(32'h8000_0001 + (i << 16) + 1'b1)
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) lut5 (
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.I0(din[0]),
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.I1(din[f1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.O(o5)
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);
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*/
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wire o6;
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wire o2_5;
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wire o2_6;
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//Randomly take out 1/4 iterations
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wire [3:0] hash = hash32(i);
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wire opt_out = |hash;
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assign dout[i] = o6 & o2_5 & o2_6 & opt_out;
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001 + (i << 16))
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) lut6 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(o6)
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);
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001 + (i << 8))
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) lut62 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o2_5),
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.O6(o2_6)
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);
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end
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endgenerate
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endmodule
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