mirror of https://github.com/openXC7/prjxray.git
65 lines
2.0 KiB
Tcl
65 lines
2.0 KiB
Tcl
create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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# Get all 6LUT and 5LUT in pblock
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# A6LUT, B6LUT, A5LUT, etc
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */*LUT]
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set grid_min_x -1
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set grid_max_x -1
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set grid_min_y -1
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set grid_max_y -1
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
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if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
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if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
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if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
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}
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set fp [open "design.txt" w]
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foreach lut $luts {
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if [get_property IS_USED $lut] {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set type [get_property TYPE $tile]
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set lut_type [get_property TYPE $lut]
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set lutc [get_cells -of_objects $lut]
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set cell_bel [get_property BEL $lutc]
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puts $fp "$type $tile $grid_x $grid_y $lut $lut_type $cell_bel"
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}
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}
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close $fp
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