mirror of https://github.com/openXC7/prjxray.git
ndimux WIP
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
4a80475db9
commit
baa9bb0d02
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@ -44,30 +44,32 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
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`define ALL1
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`ifdef ALL1
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//ok
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my_NDI1MUX_NMC31 #(.LOC("SLICE_X6Y100"))
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my_NDI1MUX_NMC31 #(.LOC("SLICE_X8Y100"))
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my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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/*
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//Can't find a valid solution
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my_NDI1MUX_NDI1 #(.LOC("SLICE_X6Y101"))
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my_NDI1MUX_NDI1 #(.LOC("SLICE_X8Y101"))
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my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8]));
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*/
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my_NDI1MUX_NI #(.LOC("SLICE_X6Y102"))
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my_NDI1MUX_NI #(.LOC("SLICE_X8Y102"))
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my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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`endif
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`define SINGLE1
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`ifdef SINGLE1
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//ok
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my_BDI1MUX_AI #(.LOC("SLICE_X8Y100"), .BEL("A6LUT"))
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my_BDI1MUX_AI(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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my_ADI1MUX_BMC31 #(.LOC("SLICE_X10Y100"))
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my_ADI1MUX_BMC31(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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//ok
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my_ADI1MUX_AI #(.LOC("SLICE_X10Y101"))
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my_ADI1MUX_AI(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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/*
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//bad
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my_BDI1MUX_BDI1 #(.LOC("SLICE_X8Y101"), .BELO("C6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BDI1(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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my_ADI1MUX_BDI1 #(.LOC("SLICE_X10Y102"))
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my_ADI1MUX_BDI1(.clk(clk), .din(din[ 80 +: 16]), .dout(dout[ 80 +: 16]));
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*/
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//ok
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my_BDI1MUX_BMC31 #(.LOC("SLICE_X8Y102"), .BELO("B6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BMC31(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
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my_BDI1MUX_DI #(.LOC("SLICE_X10Y103"))
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my_BDI1MUX_DI(.clk(clk), .din(din[ 96 +: 16]), .dout(dout[ 96 +: 16]));
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`endif
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endmodule
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@ -240,7 +242,7 @@ endmodule
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Individual mux tests
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****************************************************************************/
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module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
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module my_ADI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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@ -259,40 +261,8 @@ module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
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.D(din[7]));
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endmodule
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module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="C6LUT";
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parameter BELI="A6LUT";
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wire mc31c;
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//wire da = din[6];
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(* LOC=LOC, BEL=BELO *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[0]),
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.Q31(mc31c),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL=BELI *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[1]),
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.Q31(dout[2]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(mc31c));
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endmodule
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//ok
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module my_BDI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
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module my_ADI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="B6LUT";
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parameter BELI="A6LUT";
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@ -324,3 +294,90 @@ module my_BDI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
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endmodule
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/*
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Bad
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See my_NDI1MUX_NDI1 for a more serious effort
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*/
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module my_ADI1MUX_BDI1 (input clk, input [15:0] din, output [15:0] dout);
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parameter LOC = "";
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parameter BELO="C6LUT";
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parameter BELI="A6LUT";
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wire mc31c;
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//wire da = din[6];
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(* LOC=LOC, BEL=BELO *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[0]),
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.Q31(mc31c),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL=BELI *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[1]),
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.Q31(dout[2]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(mc31c));
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endmodule
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module my_BDI1MUX_DI (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "SLICE_X6Y100";
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wire di = din[7];
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wire wemux = din[5];
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(* LOC=LOC, BEL="D6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[0]),
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.Q31(),
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.A(din[4:0]),
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.CE(wemux),
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.CLK(clk),
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.D(di));
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(* LOC=LOC, BEL="C6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[1]),
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.Q31(),
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.A(din[4:0]),
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.CE(wemux),
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.CLK(clk),
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.D(din[7]));
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[2]),
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.Q31(),
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.A(din[4:0]),
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.CE(wemux),
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.CLK(clk),
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.D(di));
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[3]),
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.Q31(),
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.A(din[4:0]),
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.CE(wemux),
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.CLK(clk),
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.D(din[7]));
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endmodule
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