diff --git a/minitests/clb_ndi1mux/top.v b/minitests/clb_ndi1mux/top.v
index 9ff3ecd3..de5c1238 100644
--- a/minitests/clb_ndi1mux/top.v
+++ b/minitests/clb_ndi1mux/top.v
@@ -44,30 +44,32 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
 `define ALL1
 `ifdef ALL1
     //ok
-    my_NDI1MUX_NMC31 #(.LOC("SLICE_X6Y100"))
+    my_NDI1MUX_NMC31 #(.LOC("SLICE_X8Y100"))
             my_NDI1MUX_NMC31(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
     /*
     //Can't find a valid solution
-    my_NDI1MUX_NDI1 #(.LOC("SLICE_X6Y101"))
+    my_NDI1MUX_NDI1 #(.LOC("SLICE_X8Y101"))
             my_NDI1MUX_NDI1(.clk(clk), .din(din[  8 +: 32]), .dout(dout[  8 +: 8]));
     */
-    my_NDI1MUX_NI #(.LOC("SLICE_X6Y102"))
+    my_NDI1MUX_NI #(.LOC("SLICE_X8Y102"))
             my_NDI1MUX_NI(.clk(clk), .din(din[  40 +: 8]), .dout(dout[  40 +: 8]));
 `endif
 
 `define SINGLE1
 `ifdef SINGLE1
     //ok
-    my_BDI1MUX_AI #(.LOC("SLICE_X8Y100"), .BEL("A6LUT"))
-            my_BDI1MUX_AI(.clk(clk), .din(din[  64 +: 8]), .dout(dout[  64 +: 8]));
+    my_ADI1MUX_BMC31 #(.LOC("SLICE_X10Y100"))
+            my_ADI1MUX_BMC31(.clk(clk), .din(din[  64 +: 8]), .dout(dout[  64 +: 8]));
+    //ok
+    my_ADI1MUX_AI #(.LOC("SLICE_X10Y101"))
+            my_ADI1MUX_AI(.clk(clk), .din(din[  72 +: 8]), .dout(dout[  72 +: 8]));
     /*
     //bad
-    my_BDI1MUX_BDI1 #(.LOC("SLICE_X8Y101"), .BELO("C6LUT"), .BELI("A6LUT"))
-            my_BDI1MUX_BDI1(.clk(clk), .din(din[  72 +: 8]), .dout(dout[  72 +: 8]));
+    my_ADI1MUX_BDI1 #(.LOC("SLICE_X10Y102"))
+            my_ADI1MUX_BDI1(.clk(clk), .din(din[  80 +: 16]), .dout(dout[  80 +: 16]));
     */
-    //ok
-    my_BDI1MUX_BMC31 #(.LOC("SLICE_X8Y102"), .BELO("B6LUT"), .BELI("A6LUT"))
-            my_BDI1MUX_BMC31(.clk(clk), .din(din[  80 +: 8]), .dout(dout[  80 +: 8]));
+    my_BDI1MUX_DI #(.LOC("SLICE_X10Y103"))
+            my_BDI1MUX_DI(.clk(clk), .din(din[  96 +: 16]), .dout(dout[  96 +: 16]));
 `endif
 endmodule
 
@@ -240,7 +242,7 @@ endmodule
 Individual mux tests
 ****************************************************************************/
 
-module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
+module my_ADI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
     parameter LOC = "";
     parameter BEL="A6LUT";
 
@@ -259,40 +261,8 @@ module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
             .D(din[7]));
 endmodule
 
-module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout);
-    parameter LOC = "";
-    parameter BELO="C6LUT";
-    parameter BELI="A6LUT";
-
-    wire mc31c;
-    //wire da = din[6];
-
-    (* LOC=LOC, BEL=BELO *)
-    SRLC32E #(
-            .INIT(32'h00000000),
-            .IS_CLK_INVERTED(1'b0)
-        ) lutb (
-            .Q(dout[0]),
-            .Q31(mc31c),
-            .A(din[4:0]),
-            .CE(din[5]),
-            .CLK(din[6]),
-            .D(din[7]));
-    (* LOC=LOC, BEL=BELI *)
-    SRLC32E #(
-            .INIT(32'h00000000),
-            .IS_CLK_INVERTED(1'b0)
-        ) luta (
-            .Q(dout[1]),
-            .Q31(dout[2]),
-            .A(din[4:0]),
-            .CE(din[5]),
-            .CLK(din[6]),
-            .D(mc31c));
-endmodule
-
 //ok
-module my_BDI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
+module my_ADI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
     parameter LOC = "";
     parameter BELO="B6LUT";
     parameter BELI="A6LUT";
@@ -324,3 +294,90 @@ module my_BDI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
 
 endmodule
 
+/*
+Bad
+See my_NDI1MUX_NDI1 for a more serious effort
+*/
+module my_ADI1MUX_BDI1 (input clk, input [15:0] din, output [15:0] dout);
+    parameter LOC = "";
+    parameter BELO="C6LUT";
+    parameter BELI="A6LUT";
+
+    wire mc31c;
+    //wire da = din[6];
+
+    (* LOC=LOC, BEL=BELO *)
+    SRLC32E #(
+            .INIT(32'h00000000),
+            .IS_CLK_INVERTED(1'b0)
+        ) lutb (
+            .Q(dout[0]),
+            .Q31(mc31c),
+            .A(din[4:0]),
+            .CE(din[5]),
+            .CLK(din[6]),
+            .D(din[7]));
+    (* LOC=LOC, BEL=BELI *)
+    SRLC32E #(
+            .INIT(32'h00000000),
+            .IS_CLK_INVERTED(1'b0)
+        ) luta (
+            .Q(dout[1]),
+            .Q31(dout[2]),
+            .A(din[4:0]),
+            .CE(din[5]),
+            .CLK(din[6]),
+            .D(mc31c));
+endmodule
+
+module my_BDI1MUX_DI (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC = "SLICE_X6Y100";
+    wire di = din[7];
+    wire wemux = din[5];
+
+    (* LOC=LOC, BEL="D6LUT" *)
+    SRLC32E #(
+            .INIT(32'h00000000),
+            .IS_CLK_INVERTED(1'b0)
+        ) lutd (
+            .Q(dout[0]),
+            .Q31(),
+            .A(din[4:0]),
+            .CE(wemux),
+            .CLK(clk),
+            .D(di));
+    (* LOC=LOC, BEL="C6LUT" *)
+    SRLC32E #(
+            .INIT(32'h00000000),
+            .IS_CLK_INVERTED(1'b0)
+        ) lutc (
+            .Q(dout[1]),
+            .Q31(),
+            .A(din[4:0]),
+            .CE(wemux),
+            .CLK(clk),
+            .D(din[7]));
+    (* LOC=LOC, BEL="B6LUT" *)
+    SRLC32E #(
+            .INIT(32'h00000000),
+            .IS_CLK_INVERTED(1'b0)
+        ) lutb (
+            .Q(dout[2]),
+            .Q31(),
+            .A(din[4:0]),
+            .CE(wemux),
+            .CLK(clk),
+            .D(di));
+    (* LOC=LOC, BEL="A6LUT" *)
+    SRLC32E #(
+            .INIT(32'h00000000),
+            .IS_CLK_INVERTED(1'b0)
+        ) luta (
+            .Q(dout[3]),
+            .Q31(),
+            .A(din[4:0]),
+            .CE(wemux),
+            .CLK(clk),
+            .D(din[7]));
+endmodule
+