diff --git a/fuzzers/015-clb-nffmux/generate.py b/fuzzers/015-clb-nffmux/generate.py
index 45b24ab7..98b442e9 100644
--- a/fuzzers/015-clb-nffmux/generate.py
+++ b/fuzzers/015-clb-nffmux/generate.py
@@ -67,17 +67,19 @@ for loc, muxes in cache.items():
             tag = "%sFFMUX.%s" % (which, src)
             segmk.add_site_tag(loc, tag, 0)
 
+
 def bitfilter(frame_idx, bit_idx):
-    
+
     # Since the SRL32 is enabled along with DFFMUX.MC31, bits related to
     # SRL32 features are masked out.
     if (frame_idx, bit_idx) in [
         (30, 16),  # ALUT.SRL
-        ( 1, 23),  # WEMUX.CE
+        (1, 23),  # WEMUX.CE
     ]:
         return False
 
     return util.bitfilter_clb_mux(frame_idx, bit_idx)
 
+
 segmk.compile(bitfilter=bitfilter)
 segmk.write()
diff --git a/fuzzers/015-clb-nffmux/top.py b/fuzzers/015-clb-nffmux/top.py
index f5b5b9be..8cc79b72 100644
--- a/fuzzers/015-clb-nffmux/top.py
+++ b/fuzzers/015-clb-nffmux/top.py
@@ -9,16 +9,19 @@ INCREMENT = os.getenv('CLBN', 0)
 CLBN = 600 + int(INCREMENT)
 print('//Requested CLBs: %s' % str(CLBN))
 
+
 def gen_slicels():
     for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
         ['SLICEL']):
         yield site_name
 
+
 def gen_slicems():
     for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
         ['SLICEM']):
         yield site_name
 
+
 DIN_N = CLBN * 8
 DOUT_N = CLBN * 8
 
@@ -37,7 +40,7 @@ for i in range(CLBN):
 
     if use_slicem:
         loc = next(slicems)
-        variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR', 'MC31'] 
+        variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR', 'MC31']
     else:
         loc = next(slicels)
         variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR']
diff --git a/fuzzers/016-clb-noutmux/generate.py b/fuzzers/016-clb-noutmux/generate.py
index a06ff35c..07ad3716 100644
--- a/fuzzers/016-clb-noutmux/generate.py
+++ b/fuzzers/016-clb-noutmux/generate.py
@@ -87,9 +87,9 @@ def bitfilter(frame_idx, bit_idx):
         (30, 19),
         (31, 19),  # B5MA
         (30, 9),
-        (31, 8),   # A5MA
+        (31, 8),  # A5MA
         (30, 16),  # ALUT.SRL
-        ( 1, 23),  # WEMUX.CE
+        (1, 23),  # WEMUX.CE
     ]:
         return False
 
diff --git a/fuzzers/016-clb-noutmux/top.py b/fuzzers/016-clb-noutmux/top.py
index 916efc8a..2d513066 100644
--- a/fuzzers/016-clb-noutmux/top.py
+++ b/fuzzers/016-clb-noutmux/top.py
@@ -9,6 +9,7 @@ INCREMENT = os.getenv('CLBN', 0)
 CLBN = 600 + int(INCREMENT)
 print('//Requested CLBs: %s' % str(CLBN))
 
+
 def gen_slicels():
     for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
         ['SLICEL']):
@@ -20,6 +21,7 @@ def gen_slicems():
         ['SLICEM']):
         yield site_name
 
+
 DIN_N = CLBN * 8
 DOUT_N = CLBN * 8