mirror of https://github.com/openXC7/prjxray.git
clb_bffmux minitest
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
43d68d8cc8
commit
b4e57e2ed5
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@ -0,0 +1,8 @@
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/.Xil
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/design/
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/design.bit
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/design.bits
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/design.txt
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@ -0,0 +1,27 @@
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N := 3
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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all:
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bash runme.sh
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test -z $(fgrep CRITICAL vivado.log)
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segprint -z -D design.bits >design.txt
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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.PHONY: database pushdb clean
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@ -0,0 +1,7 @@
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#!/bin/bash
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set -ex
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# rm -f vivado*.log vivado*.jou
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vivado -mode batch -source runme.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103
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@ -0,0 +1,26 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,225 @@
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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//clb_BFFMUX_NO clb_BFFMUX_NO (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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clb_BFFMUX_BX clb_BFFMUX_BX (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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clb_BFFMUX_CY clb_BFFMUX_CY (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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clb_BFFMUX_F8 clb_BFFMUX_F8 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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clb_BFFMUX_O5 clb_BFFMUX_O5 (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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clb_BFFMUX_O6 clb_BFFMUX_O6 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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clb_BFFMUX_XOR clb_BFFMUX_XOR (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ]));
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endmodule
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module myLUT8 (input clk, input [7:0] din,
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output lut8o,
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//caro: XOR additional result (main output)
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//carco: CLA result (carry module additional output)
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output caro, output carco,
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output bo5, output bo6,
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output wire ff_q, //always connect to output
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input wire ff_d); //mux output net
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parameter LOC="SLICE_FIXME";
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parameter N=1;
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wire [3:0] caro_all;
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assign caro = caro_all[N];
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wire [3:0] carco_all;
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assign carco = carco_all[N];
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wire [3:0] lutno6;
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wire [3:0] lutno5;
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wire lut7bo, lut7ao;
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assign bo5 = lutno5[N];
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assign bo6 = lutno6[N];
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//Outputs does not have to be used, will stay without it
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(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
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MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
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(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(lut7bo), .I0(lutno6[3]), .I1(lutno6[2]), .S(din[6]));
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(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7a (.O(lut7ao), .I0(lutno6[1]), .I1(lutno6[0]), .S(din[6]));
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[3]),
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.O6(lutno6[3]));
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[2]),
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.O6(lutno6[2]));
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_CAFE_0000_0001)
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) lutb (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[1]),
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.O6(lutno6[1]));
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_1CE0_0000_0001)
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) luta (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[0]),
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.O6(lutno6[0]));
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//Outputs do not have to be used, will stay without them
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(caro_all), .CO(carco_all), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI());
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(* LOC=LOC, BEL="BFF", KEEP, DONT_TOUCH *)
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FDPE ff (
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.C(clk),
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.Q(ff_q),
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.CE(1'b1),
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.PRE(1'b0),
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.D(ff_d));
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endmodule
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//******************************************************************************
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//BFFMUX tests
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/*
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module clb_BFFMUX_NO (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X18Y100";
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myLUT8 #(.LOC(LOC))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(), .carco(), .bo5(), .bo6(),
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.n5ff_q());
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endmodule
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*/
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module clb_BFFMUX_BX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X18Y101";
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myLUT8 #(.LOC(LOC))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(), .carco(),
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.bo5(), .bo6(),
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.ff_q(dout[0]),
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.ff_d(din[6])); //used on MUX8:S
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endmodule
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module clb_BFFMUX_CY (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X18Y102";
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wire carco;
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myLUT8 #(.LOC(LOC))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(), .carco(carco),
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.bo5(), .bo6(),
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.ff_q(dout[0]),
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.ff_d(carco));
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endmodule
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module clb_BFFMUX_F8 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X18Y103";
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wire lut8o;
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myLUT8 #(.LOC(LOC))
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myLUT8(.clk(clk), .din(din),
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.lut8o(lut8o),
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.caro(), .carco(),
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.bo5(), .bo6(),
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.ff_q(dout[0]),
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.ff_d(lut8o));
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endmodule
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module clb_BFFMUX_O5 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X18Y104";
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wire bo5;
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myLUT8 #(.LOC(LOC))
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myLUT8(.clk(clk), .din(din),
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.lut8o(lut8o),
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.caro(), .carco(),
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.bo5(bo5), .bo6(),
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.ff_q(dout[0]),
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.ff_d(bo5));
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endmodule
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module clb_BFFMUX_O6 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X18Y105";
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wire bo6;
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myLUT8 #(.LOC(LOC))
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myLUT8(.clk(clk), .din(din),
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.lut8o(lut8o),
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.caro(), .carco(),
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.bo5(), .bo6(bo6),
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.ff_q(dout[0]),
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.ff_d(bo6));
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endmodule
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module clb_BFFMUX_XOR (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X18Y106";
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wire caro;
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myLUT8 #(.LOC(LOC))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(caro), .carco(),
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.bo5(), .bo6(bo6),
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.ff_q(dout[0]),
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.ff_d(caro));
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endmodule
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@ -5,3 +5,4 @@
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/design.txt
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@ -29,16 +29,23 @@ module top(input clk, stb, di, output do);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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clb_BOUTMUX_CY clb_BOUTMUX_CY (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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clb_BOUTMUX_F8 clb_BOUTMUX_F8 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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clb_BOUTMUX_O6 clb_BOUTMUX_O6 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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clb_BOUTMUX_O5 clb_BOUTMUX_O5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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clb_BOUTMUX_B5Q clb_BOUTMUX_B5Q (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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clb_BOUTMUX_XOR clb_BOUTMUX_XOR (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8 ]));
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//clb_BOUTMUX_NO clb_BOUTMUX_NO (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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clb_BOUTMUX_CY clb_BOUTMUX_CY (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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clb_BOUTMUX_F8 clb_BOUTMUX_F8 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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//clb_BOUTMUX_O6 clb_BOUTMUX_O6 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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clb_BOUTMUX_O5 clb_BOUTMUX_O5 (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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//clb_BOUTMUX_O56 clb_BOUTMUX_O56 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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clb_BOUTMUX_B5Q clb_BOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ]));
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clb_BOUTMUX_XOR clb_BOUTMUX_XOR (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8 ]));
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endmodule
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module myLUT8 (input clk, input [7:0] din, output lut8o, output [3:0] co, output [3:0] cout, output bo5, output bo6);
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parameter LOC="SLICE_X18Y101";
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module myLUT8 (input clk, input [7:0] din,
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output lut8o,
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output [3:0] co, output [3:0] cout, output bo5, output bo6,
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//Note: b5ff_q requires the mux and will conflict with other wires
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//Otherwise this FF drops out
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output wire [3:0] n5ff_q);
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parameter LOC="SLICE_FIXME";
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wire [3:0] lutno6;
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wire [3:0] lutno5;
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@ -46,6 +53,7 @@ module myLUT8 (input clk, input [7:0] din, output lut8o, output [3:0] co, output
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assign bo5 = lutno5[1];
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assign bo6 = lutno6[1];
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//Outputs does not have to be used, will stay without it
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(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
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MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
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(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
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@ -105,65 +113,137 @@ module myLUT8 (input clk, input [7:0] din, output lut8o, output [3:0] co, output
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.O5(lutno5[0]),
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.O6(lutno6[0]));
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//Outputs do not have to be used, will stay without them
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(co), .CO(cout), .DI(din[3:0]), .S(lutno6), .CYINIT(1'b0), .CI());
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CARRY4 carry4(.O(co), .CO(cout), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI());
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(* LOC=LOC, BEL="D5FF", KEEP, DONT_TOUCH *)
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FDPE d5ff (
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.C(clk),
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.Q(n5ff_q[3]),
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.CE(1'b1),
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.PRE(1'b0),
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.D(lutno5[3]));
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(* LOC=LOC, BEL="C5FF", KEEP, DONT_TOUCH *)
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FDPE c5ff (
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.C(clk),
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.Q(n5ff_q[2]),
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.CE(1'b1),
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.PRE(1'b0),
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.D(lutno5[2]));
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/*
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(* LOC=LOC, BEL="B5FF" *)
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FDPE ff (
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.C(clk),
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.Q(n5ff_q[1]),
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.CE(1'b1),
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//SR options
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//0 or dedicated SR
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//.PRE(1'b0), //bypass mode
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.PRE(din[0]),
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//D options
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//A: B6LUT:O5 (seems easiest)
|
||||
//B: BX => MUX8:S
|
||||
.D(lutno5[1]));
|
||||
*/
|
||||
(* LOC=LOC, BEL="B5FF", KEEP, DONT_TOUCH *)
|
||||
FDPE b5ff (
|
||||
.C(clk),
|
||||
.Q(n5ff_q[1]),
|
||||
.CE(1'b1),
|
||||
.PRE(1'b0),
|
||||
//causing routing congestion with MUX8
|
||||
//.D(1'b0));
|
||||
.D(lutno5[1]));
|
||||
|
||||
(* LOC=LOC, BEL="A5FF", KEEP, DONT_TOUCH *)
|
||||
FDPE a5ff (
|
||||
.C(clk),
|
||||
.Q(n5ff_q[0]),
|
||||
.CE(1'b1),
|
||||
.PRE(1'b0),
|
||||
.D(lutno5[0]));
|
||||
endmodule
|
||||
|
||||
//******************************************************************************
|
||||
//BOUTMUX tests
|
||||
|
||||
module clb_BOUTMUX_CY (input clk, input [7:0] din, output [7:0] dout);
|
||||
/*
|
||||
module clb_BOUTMUX_NO (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y100";
|
||||
|
||||
wire [3:0] cout;
|
||||
assign dout = cout[1];
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(), .cout(cout));
|
||||
myLUT8(.clk(clk), .din(din),
|
||||
.lut8o(),
|
||||
.co(), .cout(), .bo5(), .bo6(),
|
||||
.n5ff_q());
|
||||
endmodule
|
||||
*/
|
||||
|
||||
module clb_BOUTMUX_CY (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y101";
|
||||
|
||||
wire [3:0] cout;
|
||||
assign dout[0] = cout[1];
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din),
|
||||
.lut8o(),
|
||||
.co(), .cout(cout), .bo5(), .bo6(),
|
||||
.n5ff_q());
|
||||
endmodule
|
||||
|
||||
//clb_BOUTMUX_F8: already have above as clb_LUT8
|
||||
module clb_BOUTMUX_F8 (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y101";
|
||||
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(dout[0]), .cout());
|
||||
endmodule
|
||||
|
||||
/*
|
||||
FIXME: need to force it to use both X and O6
|
||||
*/
|
||||
module clb_BOUTMUX_O6 (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y102";
|
||||
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(), .cout());
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(dout[0]), .co(), .cout(), .bo5(), .bo6());
|
||||
endmodule
|
||||
|
||||
module clb_BOUTMUX_O5 (input clk, input [7:0] din, output [7:0] dout);
|
||||
/*
|
||||
//FIXME: need to force it to use both X and O6
|
||||
module clb_BOUTMUX_O6 (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y103";
|
||||
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(), .cout(), .bo5(dout[1]), .bo6(dout[0]));
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(), .co(), .cout(), .bo5(), .bo6());
|
||||
endmodule
|
||||
*/
|
||||
|
||||
module clb_BOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout);
|
||||
module clb_BOUTMUX_O5 (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y104";
|
||||
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din), .cout());
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(), .co(), .cout(), .bo5(dout[1]), .bo6());
|
||||
endmodule
|
||||
|
||||
(* LOC=LOC, BEL="B5FF" *)
|
||||
FDPE ff (
|
||||
.C(clk),
|
||||
.Q(dout[1]),
|
||||
.CE(din[0]),
|
||||
.PRE(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
/*
|
||||
No observed difference to O5
|
||||
The buffer doesn't give me any additional info
|
||||
module clb_BOUTMUX_O56 (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y105";
|
||||
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din), .lut8o(), .co(), .cout(), .bo5(dout[1]), .bo6(dout[0]));
|
||||
endmodule
|
||||
*/
|
||||
|
||||
module clb_BOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y106";
|
||||
wire [3:0] n5ff_q;
|
||||
assign dout[0] = n5ff_q[1];
|
||||
|
||||
myLUT8 #(.LOC(LOC))
|
||||
myLUT8(.clk(clk), .din(din),
|
||||
.lut8o(),
|
||||
.co(), .cout(), .bo5(), .bo6(),
|
||||
.n5ff_q(n5ff_q));
|
||||
endmodule
|
||||
|
||||
module clb_BOUTMUX_XOR (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X18Y105";
|
||||
parameter LOC="SLICE_X18Y107";
|
||||
|
||||
//Shady connections, just enough to keep it placed
|
||||
wire [3:0] co;
|
||||
|
|
@ -173,3 +253,4 @@ module clb_BOUTMUX_XOR (input clk, input [7:0] din, output [7:0] dout);
|
|||
myLUT8(.clk(clk), .din(din), .lut8o(), .co(co), .cout(), .bo5(), .bo6());
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue