From b4e57e2ed519db3e85fc7b6163002dff6290f0e4 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Mon, 4 Dec 2017 17:38:53 -0800 Subject: [PATCH] clb_bffmux minitest Signed-off-by: John McMaster Signed-off-by: Tim 'mithro' Ansell --- minitests/clb_bffmux/.gitignore | 8 ++ minitests/clb_bffmux/Makefile | 27 ++++ minitests/clb_bffmux/README.txt | 0 minitests/clb_bffmux/runme.sh | 7 + minitests/clb_bffmux/runme.tcl | 26 ++++ minitests/clb_bffmux/top.v | 225 +++++++++++++++++++++++++++++++ minitests/clb_boutmux/.gitignore | 1 + minitests/clb_boutmux/top.v | 155 ++++++++++++++++----- 8 files changed, 412 insertions(+), 37 deletions(-) create mode 100644 minitests/clb_bffmux/.gitignore create mode 100644 minitests/clb_bffmux/Makefile create mode 100644 minitests/clb_bffmux/README.txt create mode 100755 minitests/clb_bffmux/runme.sh create mode 100644 minitests/clb_bffmux/runme.tcl create mode 100644 minitests/clb_bffmux/top.v diff --git a/minitests/clb_bffmux/.gitignore b/minitests/clb_bffmux/.gitignore new file mode 100644 index 00000000..82a01aa0 --- /dev/null +++ b/minitests/clb_bffmux/.gitignore @@ -0,0 +1,8 @@ +/.Xil +/design/ +/design.bit +/design.bits +/design.dcp +/usage_statistics_webtalk.* +/vivado* +/design.txt diff --git a/minitests/clb_bffmux/Makefile b/minitests/clb_bffmux/Makefile new file mode 100644 index 00000000..3d18a8ab --- /dev/null +++ b/minitests/clb_bffmux/Makefile @@ -0,0 +1,27 @@ +N := 3 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +all: + bash runme.sh + test -z $(fgrep CRITICAL vivado.log) + segprint -z -D design.bits >design.txt + +database: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS)) + +pushdb: + ${XRAY_MERGEDDB} clbll_l seg_clblx.segbits + ${XRAY_MERGEDDB} clbll_r seg_clblx.segbits + ${XRAY_MERGEDDB} clblm_l seg_clblx.segbits + ${XRAY_MERGEDDB} clblm_r seg_clblx.segbits + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil + +.PHONY: database pushdb clean + diff --git a/minitests/clb_bffmux/README.txt b/minitests/clb_bffmux/README.txt new file mode 100644 index 00000000..e69de29b diff --git a/minitests/clb_bffmux/runme.sh b/minitests/clb_bffmux/runme.sh new file mode 100755 index 00000000..536f2346 --- /dev/null +++ b/minitests/clb_bffmux/runme.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +set -ex +# rm -f vivado*.log vivado*.jou +vivado -mode batch -source runme.tcl +${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit +#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103 diff --git a/minitests/clb_bffmux/runme.tcl b/minitests/clb_bffmux/runme.tcl new file mode 100644 index 00000000..86162f92 --- /dev/null +++ b/minitests/clb_bffmux/runme.tcl @@ -0,0 +1,26 @@ +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi] +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit + diff --git a/minitests/clb_bffmux/top.v b/minitests/clb_bffmux/top.v new file mode 100644 index 00000000..108251e3 --- /dev/null +++ b/minitests/clb_bffmux/top.v @@ -0,0 +1,225 @@ +module top(input clk, stb, di, output do); + localparam integer DIN_N = 256; + localparam integer DOUT_N = 256; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + roi roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule + +module roi(input clk, input [255:0] din, output [255:0] dout); + //clb_BFFMUX_NO clb_BFFMUX_NO (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + clb_BFFMUX_BX clb_BFFMUX_BX (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + clb_BFFMUX_CY clb_BFFMUX_CY (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + clb_BFFMUX_F8 clb_BFFMUX_F8 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + clb_BFFMUX_O5 clb_BFFMUX_O5 (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + clb_BFFMUX_O6 clb_BFFMUX_O6 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + clb_BFFMUX_XOR clb_BFFMUX_XOR (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ])); +endmodule + +module myLUT8 (input clk, input [7:0] din, + output lut8o, + //caro: XOR additional result (main output) + //carco: CLA result (carry module additional output) + output caro, output carco, + output bo5, output bo6, + output wire ff_q, //always connect to output + input wire ff_d); //mux output net + parameter LOC="SLICE_FIXME"; + parameter N=1; + + wire [3:0] caro_all; + assign caro = caro_all[N]; + wire [3:0] carco_all; + assign carco = carco_all[N]; + wire [3:0] lutno6; + wire [3:0] lutno5; + wire lut7bo, lut7ao; + assign bo5 = lutno5[N]; + assign bo6 = lutno6[N]; + + //Outputs does not have to be used, will stay without it + (* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *) + MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6])); + (* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *) + MUXF7 mux7b (.O(lut7bo), .I0(lutno6[3]), .I1(lutno6[2]), .S(din[6])); + (* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *) + MUXF7 mux7a (.O(lut7ao), .I0(lutno6[1]), .I1(lutno6[0]), .S(din[6])); + + (* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *) + LUT6_2 #( + .INIT(64'h8000_DEAD_0000_0001) + ) lutd ( + .I0(din[0]), + .I1(din[1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .I5(din[5]), + .O5(lutno5[3]), + .O6(lutno6[3])); + + (* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *) + LUT6_2 #( + .INIT(64'h8000_BEEF_0000_0001) + ) lutc ( + .I0(din[0]), + .I1(din[1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .I5(din[5]), + .O5(lutno5[2]), + .O6(lutno6[2])); + + (* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *) + LUT6_2 #( + .INIT(64'h8000_CAFE_0000_0001) + ) lutb ( + .I0(din[0]), + .I1(din[1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .I5(din[5]), + .O5(lutno5[1]), + .O6(lutno6[1])); + + (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *) + LUT6_2 #( + .INIT(64'h8000_1CE0_0000_0001) + ) luta ( + .I0(din[0]), + .I1(din[1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .I5(din[5]), + .O5(lutno5[0]), + .O6(lutno6[0])); + + //Outputs do not have to be used, will stay without them + (* LOC=LOC, KEEP, DONT_TOUCH *) + CARRY4 carry4(.O(caro_all), .CO(carco_all), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI()); + + (* LOC=LOC, BEL="BFF", KEEP, DONT_TOUCH *) + FDPE ff ( + .C(clk), + .Q(ff_q), + .CE(1'b1), + .PRE(1'b0), + .D(ff_d)); +endmodule + +//****************************************************************************** +//BFFMUX tests + +/* +module clb_BFFMUX_NO (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y100"; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(), + .caro(), .carco(), .bo5(), .bo6(), + .n5ff_q()); +endmodule +*/ + +module clb_BFFMUX_BX (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y101"; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(), + .caro(), .carco(), + .bo5(), .bo6(), + .ff_q(dout[0]), + .ff_d(din[6])); //used on MUX8:S + +endmodule + +module clb_BFFMUX_CY (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y102"; + wire carco; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(), + .caro(), .carco(carco), + .bo5(), .bo6(), + .ff_q(dout[0]), + .ff_d(carco)); +endmodule + +module clb_BFFMUX_F8 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y103"; + wire lut8o; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(lut8o), + .caro(), .carco(), + .bo5(), .bo6(), + .ff_q(dout[0]), + .ff_d(lut8o)); +endmodule + +module clb_BFFMUX_O5 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y104"; + wire bo5; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(lut8o), + .caro(), .carco(), + .bo5(bo5), .bo6(), + .ff_q(dout[0]), + .ff_d(bo5)); +endmodule + +module clb_BFFMUX_O6 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y105"; + wire bo6; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(lut8o), + .caro(), .carco(), + .bo5(), .bo6(bo6), + .ff_q(dout[0]), + .ff_d(bo6)); +endmodule + +module clb_BFFMUX_XOR (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y106"; + wire caro; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(), + .caro(caro), .carco(), + .bo5(), .bo6(bo6), + .ff_q(dout[0]), + .ff_d(caro)); +endmodule + diff --git a/minitests/clb_boutmux/.gitignore b/minitests/clb_boutmux/.gitignore index bc8f2f32..82a01aa0 100644 --- a/minitests/clb_boutmux/.gitignore +++ b/minitests/clb_boutmux/.gitignore @@ -5,3 +5,4 @@ /design.dcp /usage_statistics_webtalk.* /vivado* +/design.txt diff --git a/minitests/clb_boutmux/top.v b/minitests/clb_boutmux/top.v index 1e828f15..83fd65af 100644 --- a/minitests/clb_boutmux/top.v +++ b/minitests/clb_boutmux/top.v @@ -29,16 +29,23 @@ module top(input clk, stb, di, output do); endmodule module roi(input clk, input [255:0] din, output [255:0] dout); - clb_BOUTMUX_CY clb_BOUTMUX_CY (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - clb_BOUTMUX_F8 clb_BOUTMUX_F8 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - clb_BOUTMUX_O6 clb_BOUTMUX_O6 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - clb_BOUTMUX_O5 clb_BOUTMUX_O5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - clb_BOUTMUX_B5Q clb_BOUTMUX_B5Q (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - clb_BOUTMUX_XOR clb_BOUTMUX_XOR (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8 ])); + //clb_BOUTMUX_NO clb_BOUTMUX_NO (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + clb_BOUTMUX_CY clb_BOUTMUX_CY (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + clb_BOUTMUX_F8 clb_BOUTMUX_F8 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + //clb_BOUTMUX_O6 clb_BOUTMUX_O6 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + clb_BOUTMUX_O5 clb_BOUTMUX_O5 (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + //clb_BOUTMUX_O56 clb_BOUTMUX_O56 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + clb_BOUTMUX_B5Q clb_BOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ])); + clb_BOUTMUX_XOR clb_BOUTMUX_XOR (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8 ])); endmodule -module myLUT8 (input clk, input [7:0] din, output lut8o, output [3:0] co, output [3:0] cout, output bo5, output bo6); - parameter LOC="SLICE_X18Y101"; +module myLUT8 (input clk, input [7:0] din, + output lut8o, + output [3:0] co, output [3:0] cout, output bo5, output bo6, + //Note: b5ff_q requires the mux and will conflict with other wires + //Otherwise this FF drops out + output wire [3:0] n5ff_q); + parameter LOC="SLICE_FIXME"; wire [3:0] lutno6; wire [3:0] lutno5; @@ -46,6 +53,7 @@ module myLUT8 (input clk, input [7:0] din, output lut8o, output [3:0] co, output assign bo5 = lutno5[1]; assign bo6 = lutno6[1]; + //Outputs does not have to be used, will stay without it (* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *) MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6])); (* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *) @@ -105,65 +113,137 @@ module myLUT8 (input clk, input [7:0] din, output lut8o, output [3:0] co, output .O5(lutno5[0]), .O6(lutno6[0])); + //Outputs do not have to be used, will stay without them (* LOC=LOC, KEEP, DONT_TOUCH *) - CARRY4 carry4(.O(co), .CO(cout), .DI(din[3:0]), .S(lutno6), .CYINIT(1'b0), .CI()); + CARRY4 carry4(.O(co), .CO(cout), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI()); + + (* LOC=LOC, BEL="D5FF", KEEP, DONT_TOUCH *) + FDPE d5ff ( + .C(clk), + .Q(n5ff_q[3]), + .CE(1'b1), + .PRE(1'b0), + .D(lutno5[3])); + + (* LOC=LOC, BEL="C5FF", KEEP, DONT_TOUCH *) + FDPE c5ff ( + .C(clk), + .Q(n5ff_q[2]), + .CE(1'b1), + .PRE(1'b0), + .D(lutno5[2])); + + /* + (* LOC=LOC, BEL="B5FF" *) + FDPE ff ( + .C(clk), + .Q(n5ff_q[1]), + .CE(1'b1), + //SR options + //0 or dedicated SR + //.PRE(1'b0), //bypass mode + .PRE(din[0]), + //D options + //A: B6LUT:O5 (seems easiest) + //B: BX => MUX8:S + .D(lutno5[1])); + */ + (* LOC=LOC, BEL="B5FF", KEEP, DONT_TOUCH *) + FDPE b5ff ( + .C(clk), + .Q(n5ff_q[1]), + .CE(1'b1), + .PRE(1'b0), + //causing routing congestion with MUX8 + //.D(1'b0)); + .D(lutno5[1])); + + (* LOC=LOC, BEL="A5FF", KEEP, DONT_TOUCH *) + FDPE a5ff ( + .C(clk), + .Q(n5ff_q[0]), + .CE(1'b1), + .PRE(1'b0), + .D(lutno5[0])); endmodule //****************************************************************************** //BOUTMUX tests -module clb_BOUTMUX_CY (input clk, input [7:0] din, output [7:0] dout); +/* +module clb_BOUTMUX_NO (input clk, input [7:0] din, output [7:0] dout); parameter LOC="SLICE_X18Y100"; - wire [3:0] cout; - assign dout = cout[1]; myLUT8 #(.LOC(LOC)) - myLUT8(.clk(clk), .din(din), .lut8o(), .cout(cout)); + myLUT8(.clk(clk), .din(din), + .lut8o(), + .co(), .cout(), .bo5(), .bo6(), + .n5ff_q()); +endmodule +*/ + +module clb_BOUTMUX_CY (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y101"; + + wire [3:0] cout; + assign dout[0] = cout[1]; + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(), + .co(), .cout(cout), .bo5(), .bo6(), + .n5ff_q()); endmodule //clb_BOUTMUX_F8: already have above as clb_LUT8 module clb_BOUTMUX_F8 (input clk, input [7:0] din, output [7:0] dout); - parameter LOC="SLICE_X18Y101"; - - myLUT8 #(.LOC(LOC)) - myLUT8(.clk(clk), .din(din), .lut8o(dout[0]), .cout()); -endmodule - -/* -FIXME: need to force it to use both X and O6 -*/ -module clb_BOUTMUX_O6 (input clk, input [7:0] din, output [7:0] dout); parameter LOC="SLICE_X18Y102"; myLUT8 #(.LOC(LOC)) - myLUT8(.clk(clk), .din(din), .lut8o(), .cout()); + myLUT8(.clk(clk), .din(din), .lut8o(dout[0]), .co(), .cout(), .bo5(), .bo6()); endmodule -module clb_BOUTMUX_O5 (input clk, input [7:0] din, output [7:0] dout); +/* +//FIXME: need to force it to use both X and O6 +module clb_BOUTMUX_O6 (input clk, input [7:0] din, output [7:0] dout); parameter LOC="SLICE_X18Y103"; myLUT8 #(.LOC(LOC)) - myLUT8(.clk(clk), .din(din), .lut8o(), .cout(), .bo5(dout[1]), .bo6(dout[0])); + myLUT8(.clk(clk), .din(din), .lut8o(), .co(), .cout(), .bo5(), .bo6()); endmodule +*/ -module clb_BOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout); +module clb_BOUTMUX_O5 (input clk, input [7:0] din, output [7:0] dout); parameter LOC="SLICE_X18Y104"; myLUT8 #(.LOC(LOC)) - myLUT8(.clk(clk), .din(din), .cout()); + myLUT8(.clk(clk), .din(din), .lut8o(), .co(), .cout(), .bo5(dout[1]), .bo6()); +endmodule - (* LOC=LOC, BEL="B5FF" *) - FDPE ff ( - .C(clk), - .Q(dout[1]), - .CE(din[0]), - .PRE(din[1]), - .D(din[2]) - ); +/* +No observed difference to O5 +The buffer doesn't give me any additional info +module clb_BOUTMUX_O56 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y105"; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), .lut8o(), .co(), .cout(), .bo5(dout[1]), .bo6(dout[0])); +endmodule +*/ + +module clb_BOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_X18Y106"; + wire [3:0] n5ff_q; + assign dout[0] = n5ff_q[1]; + + myLUT8 #(.LOC(LOC)) + myLUT8(.clk(clk), .din(din), + .lut8o(), + .co(), .cout(), .bo5(), .bo6(), + .n5ff_q(n5ff_q)); endmodule module clb_BOUTMUX_XOR (input clk, input [7:0] din, output [7:0] dout); - parameter LOC="SLICE_X18Y105"; + parameter LOC="SLICE_X18Y107"; //Shady connections, just enough to keep it placed wire [3:0] co; @@ -173,3 +253,4 @@ module clb_BOUTMUX_XOR (input clk, input [7:0] din, output [7:0] dout); myLUT8(.clk(clk), .din(din), .lut8o(), .co(co), .cout(), .bo5(), .bo6()); endmodule +