From b39e39315dc3c44e5ac645f5c81d400a49130f17 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 6 Nov 2018 08:30:07 -0800 Subject: [PATCH] Add option to output ignored wires and add ignored wires for kintex7. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/074-dump_all/analyze_errors.py | 94 ++++++++----- .../074-dump_all/kintex7_ignored_wires.txt | 132 ++++++++++++++++++ 2 files changed, 194 insertions(+), 32 deletions(-) create mode 100644 fuzzers/074-dump_all/kintex7_ignored_wires.txt diff --git a/fuzzers/074-dump_all/analyze_errors.py b/fuzzers/074-dump_all/analyze_errors.py index 137267d8..061c9e5f 100644 --- a/fuzzers/074-dump_all/analyze_errors.py +++ b/fuzzers/074-dump_all/analyze_errors.py @@ -1,40 +1,70 @@ import json -with open('output/error_nodes.json') as f: - flat_error_nodes = json.load(f) +import argparse -error_nodes = {} -for node, raw_node, generated_nodes in flat_error_nodes: - if node not in error_nodes: - error_nodes[node] = { - 'raw_node': set(raw_node), - 'generated_nodes': set(), - } - assert error_nodes[node]['raw_node'] == set(raw_node) - error_nodes[node]['generated_nodes'].add(tuple(sorted(generated_nodes))) +def main(): + parser = argparse.ArgumentParser(description="") -for node, error in error_nodes.items(): - combined_generated_nodes = set() - for generated_node in error['generated_nodes']: - combined_generated_nodes |= set(generated_node) + parser.add_argument('--error_nodes', default='output/error_nodes.json') + parser.add_argument('--output_ignore_list', action='store_true') - assert error['raw_node'] == combined_generated_nodes, (node, error) + args = parser.parse_args() - good_node = max(error['generated_nodes'], key=lambda x: len(x)) - bad_nodes = error['generated_nodes'] - set((good_node, )) + with open(args.error_nodes) as f: + flat_error_nodes = json.load(f) - if max(len(generated_node) for generated_node in bad_nodes) > 1: - assert False, node - else: - not_pcie = False - for generated_node in bad_nodes: - for wire in generated_node: - if not wire.startswith('PCIE'): - not_pcie = True - if not_pcie: - #print(node, good_node, map(tuple, bad_nodes)) - print(repr((node, tuple(map(tuple, bad_nodes))))) - pass + error_nodes = {} + for node, raw_node, generated_nodes in flat_error_nodes: + if node not in error_nodes: + error_nodes[node] = { + 'raw_node': set(raw_node), + 'generated_nodes': set(), + } + + assert error_nodes[node]['raw_node'] == set(raw_node) + error_nodes[node]['generated_nodes'].add( + tuple(sorted(generated_nodes))) + + ignored_wires = set() + + for node, error in error_nodes.items(): + combined_generated_nodes = set() + for generated_node in error['generated_nodes']: + combined_generated_nodes |= set(generated_node) + + # Make sure there are not extra wires in nodes. + assert error['raw_node'] == combined_generated_nodes, (node, error) + + good_node = max(error['generated_nodes'], key=lambda x: len(x)) + bad_nodes = error['generated_nodes'] - set((good_node, )) + + if args.output_ignore_list: + for generated_node in bad_nodes: + for wire in generated_node: + ignored_wires.add(wire) + + continue + + if max(len(generated_node) for generated_node in bad_nodes) > 1: + assert False, node else: - #print(repr((node, map(tuple, bad_nodes)))) - pass + not_pcie = False + for generated_node in bad_nodes: + for wire in generated_node: + if not wire.startswith('PCIE'): + not_pcie = True + if not_pcie: + #print(node, good_node, map(tuple, bad_nodes)) + print(repr((node, tuple(map(tuple, bad_nodes))))) + pass + else: + #print(repr((node, map(tuple, bad_nodes)))) + pass + + if args.output_ignore_list: + for wire in ignored_wires: + print(wire) + + +if __name__ == '__main__': + main() diff --git a/fuzzers/074-dump_all/kintex7_ignored_wires.txt b/fuzzers/074-dump_all/kintex7_ignored_wires.txt new file mode 100644 index 00000000..a2640a25 --- /dev/null +++ b/fuzzers/074-dump_all/kintex7_ignored_wires.txt @@ -0,0 +1,132 @@ +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X43Y43/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y31/RIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y135/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_X0Y45/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X43Y57/RIOI_I2GCLK_BOT1 +CMT_TOP_R_LOWER_T_X8Y18/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X43Y93/RIOI_I2GCLK_TOP1 +LIOI3_X0Y59/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_TOP1 +LIOI3_X0Y179/LIOI_I2GCLK_TOP1 +RIOI_X43Y71/RIOI_I2GCLK_BOT1 +LIOI3_X0Y9/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_BOT1 +CMT_TOP_L_UPPER_B_X108Y83/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_TOP1 +LIOI3_X0Y79/LIOI_I2GCLK_TOP1 +LIOI3_X0Y191/LIOI_I2GCLK_TOP1 +LIOI3_X0Y195/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_TOP1 +RIOI_X43Y9/RIOI_I2GCLK_BOT1 +RIOI_X43Y83/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_TOP1 +RIOI_X43Y17/RIOI_I2GCLK_TOP1 +LIOI3_X0Y17/LIOI_I2GCLK_TOP1 +RIOI_X43Y41/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_BOT1 +LIOI3_X0Y159/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y19/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X43Y69/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_TOP1 +RIOI_X43Y33/RIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X43Y13/RIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y31/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_BOT1 +RIOI_X43Y95/RIOI_I2GCLK_BOT1 +LIOI3_X0Y21/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_BOT1 +LIOI3_X0Y83/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_BOT1 +RIOI_X43Y59/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_TOP1 +LIOI3_X0Y145/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_TOP1 +LIOI3_X0Y167/LIOI_I2GCLK_TOP1 +LIOI3_X0Y105/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_TOP1 +LIOI3_X0Y171/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X43Y19/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y81/RIOI_I2GCLK_TOP1 +LIOI3_X0Y29/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_TOP1 +CMT_TOP_L_LOWER_T_X108Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTESRC_X43Y57/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y43/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X43Y37/RIOI_I2GCLK_TOP1 +LIOI3_X0Y33/LIOI_I2GCLK_BOT1 +RIOI_X43Y45/RIOI_I2GCLK_BOT1 +RIOI_X43Y55/RIOI_I2GCLK_TOP1 +LIOI3_X0Y71/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X43Y87/RIOI_I2GCLK_BOT1 +CMT_TOP_L_LOWER_T_X108Y18/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTESRC_X43Y81/RIOI_I2GCLK_BOT1 +CMT_TOP_R_LOWER_T_X8Y122/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_X0Y91/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y7/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y7/RIOI_I2GCLK_TOP1 +LIOI3_X0Y183/LIOI_I2GCLK_BOT1 +RIOI_X43Y67/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_TOP1 +LIOI3_X0Y109/LIOI_I2GCLK_BOT1 +RIOI_X43Y21/RIOI_I2GCLK_BOT1 +LIOI3_X0Y67/LIOI_I2GCLK_TOP1 +LIOI3_X0Y121/LIOI_I2GCLK_BOT1 +RIOI_X43Y5/RIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y174/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTESRC_X43Y93/RIOI_I2GCLK_BOT1 +LIOI3_X0Y129/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y69/RIOI_I2GCLK_TOP1 +LIOI3_X0Y117/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_TOP1 +RIOI_X43Y91/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y187/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_X43Y29/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_TOP1 +LIOI3_X0Y55/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X43Y87/RIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X43Y63/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_BOT1 +LIOI3_X0Y141/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_TOP1 +RIOI_X43Y79/RIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X43Y37/RIOI_I2GCLK_BOT1 +CMT_TOP_R_LOWER_T_X8Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTETERM_X43Y63/RIOI_I2GCLK_BOT1 +LIOI3_X0Y41/LIOI_I2GCLK_TOP1 +LIOI3_X0Y155/LIOI_I2GCLK_TOP1 +LIOI3_X0Y95/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X43Y13/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X43Y31/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y83/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_BOT1 +LIOI3_X0Y133/LIOI_I2GCLK_BOT1 +CMT_TOP_L_UPPER_B_X108Y31/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_TOP1 +LIOI3_X0Y5/LIOI_I2GCLK_TOP1