mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1046 from antmicro/assert_zynq_bits
fuzzers: 038-cfg: Add always on bit for Zynq
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commit
b07e71787d
8
Makefile
8
Makefile
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@ -135,11 +135,9 @@ db-extras-kintex7:
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db-extras-zynq7:
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+source minitests/roi_harness/zybo-swbut.sh && $(MAKE) -C fuzzers part_only
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# TODO(#746): Zybo harness is missing some bits, disable automatic harness
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# generation.
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#+source minitests/roi_harness/zybo-swbut.sh && \
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# $(MAKE) -C minitests/roi_harness \
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# HARNESS_DIR=database/artix7/harness/zybo/swbut run
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+source minitests/roi_harness/zybo-swbut.sh && \
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$(MAKE) -C minitests/roi_harness \
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HARNESS_DIR=database/artix7/harness/zybo/swbut run
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db-check:
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@true
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@ -5,6 +5,11 @@ database: build/segbits_cfg.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_cfg.rdb \
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--seg-fn-out build/segbits_cfg.db
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# Some of the bits in Zynq seem to be always set
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# see https://github.com/SymbiFlow/prjxray/issues/746
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ifeq (${XRAY_DATABASE}, zynq7)
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python3 add_constant_bits.py build/segbits_cfg.db
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endif
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build/segbits_cfg.rdb: $(SPECIMENS_OK)
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@ -0,0 +1,25 @@
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"""
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Add bits that are considered always on to the db file.
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This script is Zynq specific.
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There are three bits that are present in all Zynq bitstreams.
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The investigation that was done to reach this conclusion is captured on GH
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(https://github.com/SymbiFlow/prjxray/issues/746)
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In brief, these bits seem to be bitstream properties related,
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but no evidence of this could be found.
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Due to the fact that the base address of these bits is the same as for the
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CFG_CENTER_MID tile it has been decided to append the bits to its db file.
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"""
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import sys
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constant_bits = {
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"CFG_CENTER_MID.ALWAYS_ON_PROP1": "26_2206",
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"CFG_CENTER_MID.ALWAYS_ON_PROP2": "26_2207",
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"CFG_CENTER_MID.ALWAYS_ON_PROP3": "27_2205"
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}
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with open(sys.argv[1], "a") as f:
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for bit_name, bit_value in constant_bits.items():
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f.write(bit_name + " " + bit_value + "\n")
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