From f71956225a6cd9703ecbfe4f9ca302fff3b5011e Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Mon, 9 Sep 2019 14:56:11 +0200 Subject: [PATCH 1/3] fuzzers: 038-cfg: Add always on bit for Zynq Signed-off-by: Tomasz Michalak --- fuzzers/038-cfg/Makefile | 5 +++++ fuzzers/038-cfg/add_constant_bits.py | 11 +++++++++++ 2 files changed, 16 insertions(+) create mode 100644 fuzzers/038-cfg/add_constant_bits.py diff --git a/fuzzers/038-cfg/Makefile b/fuzzers/038-cfg/Makefile index 4b2c308c..360ecab3 100644 --- a/fuzzers/038-cfg/Makefile +++ b/fuzzers/038-cfg/Makefile @@ -5,6 +5,11 @@ database: build/segbits_cfg.rdb ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \ --seg-fn-in build/segbits_cfg.rdb \ --seg-fn-out build/segbits_cfg.db +# Some of the bits in Zynq seem to be always set +# see https://github.com/SymbiFlow/prjxray/issues/746 +ifeq (${XRAY_DATABASE}, zynq7) + python3 add_constant_bits.py build/segbits_cfg.db +endif build/segbits_cfg.rdb: $(SPECIMENS_OK) diff --git a/fuzzers/038-cfg/add_constant_bits.py b/fuzzers/038-cfg/add_constant_bits.py new file mode 100644 index 00000000..89f68d7b --- /dev/null +++ b/fuzzers/038-cfg/add_constant_bits.py @@ -0,0 +1,11 @@ +import sys + +constant_bits = { + "CFG_CENTER_MID.ALWAYS_ON_PROP1": "26_2206", + "CFG_CENTER_MID.ALWAYS_ON_PROP2": "26_2207", + "CFG_CENTER_MID.ALWAYS_ON_PROP3": "27_2205" +} + +with open(sys.argv[1], "a") as f: + for bit_name, bit_value in constant_bits.items(): + f.write(bit_name + " " + bit_value + "\n") From 50d8c368c873c808597a73e22e3b547907e57027 Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Mon, 9 Sep 2019 15:12:44 +0200 Subject: [PATCH 2/3] Re-enable harness generation for Zynq Signed-off-by: Tomasz Michalak --- Makefile | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 73a04051..12be9a41 100644 --- a/Makefile +++ b/Makefile @@ -135,11 +135,9 @@ db-extras-kintex7: db-extras-zynq7: +source minitests/roi_harness/zybo-swbut.sh && $(MAKE) -C fuzzers part_only - # TODO(#746): Zybo harness is missing some bits, disable automatic harness - # generation. - #+source minitests/roi_harness/zybo-swbut.sh && \ - # $(MAKE) -C minitests/roi_harness \ - # HARNESS_DIR=database/artix7/harness/zybo/swbut run + +source minitests/roi_harness/zybo-swbut.sh && \ + $(MAKE) -C minitests/roi_harness \ + HARNESS_DIR=database/artix7/harness/zybo/swbut run db-check: @true From 5238fed5b5557b8a282a9120380eee01abb49bc5 Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Tue, 10 Sep 2019 08:59:29 +0200 Subject: [PATCH 3/3] Add background to script's purpose Signed-off-by: Tomasz Michalak --- fuzzers/038-cfg/add_constant_bits.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/fuzzers/038-cfg/add_constant_bits.py b/fuzzers/038-cfg/add_constant_bits.py index 89f68d7b..4730b30b 100644 --- a/fuzzers/038-cfg/add_constant_bits.py +++ b/fuzzers/038-cfg/add_constant_bits.py @@ -1,3 +1,17 @@ +""" +Add bits that are considered always on to the db file. + +This script is Zynq specific. + +There are three bits that are present in all Zynq bitstreams. +The investigation that was done to reach this conclusion is captured on GH +(https://github.com/SymbiFlow/prjxray/issues/746) +In brief, these bits seem to be bitstream properties related, +but no evidence of this could be found. +Due to the fact that the base address of these bits is the same as for the +CFG_CENTER_MID tile it has been decided to append the bits to its db file. +""" + import sys constant_bits = {