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Merge pull request #1466 from litghost/add_ram36_in_use_feature 

Add BRAM36_IN_USE feature.
This commit is contained in:
litghost 2020-10-23 07:24:17 -07:00 committed by GitHub
parent 34043d1b3d 0deee961eb
commit aff076b47d
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 169 additions and 67 deletions
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2
fuzzers/027-bram36-config/Makefile
View File

@ -7,7 +7,7 @@
# SPDX-License-Identifier: ISC # SPDX-License-Identifier: ISC
# read/write width is relatively slow to resolve # read/write width is relatively slow to resolve
# Even slower with multi bit masks... # Even slower with multi bit masks...
N ?= 2 N ?= 10
include ../fuzzer.mk include ../fuzzer.mk

16
fuzzers/027-bram36-config/generate.py
View File

@ -21,7 +21,7 @@ def write_ram_ext_tags(segmk, tile_param):
segmk.add_site_tag( segmk.add_site_tag(
tile_param['site'], "{}_{}".format(param, opt), set_val == opt) tile_param['site'], "{}_{}".format(param, opt), set_val == opt)
segmk.add_site_tag( segmk.add_site_tag(
tile_param['site'], "{}_NONE_OR_UPPER".format(param, opt), tile_param['site'], "{}_NONE_OR_UPPER".format(param),
set_val != "LOWER") set_val != "LOWER")
@ -33,12 +33,16 @@ def main():
params = json.load(f) params = json.load(f)
for tile_param in params: for tile_param in params:
write_ram_ext_tags(segmk, tile_param) if tile_param['BRAM36_IN_USE']:
write_ram_ext_tags(segmk, tile_param)
segmk.add_site_tag( segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 1)
tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ']) segmk.add_site_tag(
segmk.add_site_tag( tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ'])
tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE']) segmk.add_site_tag(
tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE'])
else:
segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 0)
segmk.compile() segmk.compile()
segmk.write() segmk.write()

218
fuzzers/027-bram36-config/top.py
View File

@ -12,14 +12,33 @@ import os
import random import random
import json import json
random.seed(int(os.getenv("SEED"), 16)) random.seed(int(os.getenv("SEED"), 16))
from prjxray.db import Database
from prjxray import util from prjxray import util
from prjxray import verilog from prjxray import verilog
def gen_bram36(): def gen_bram36(grid):
for tile_name, site_name, _site_type in util.get_roi().gen_sites( for tile_name in grid.tiles():
['RAMBFIFO36E1']): loc = grid.loc_of_tilename(tile_name)
yield tile_name, site_name
gridinfo = grid.gridinfo_at_loc(loc)
found = False
for site_name, site_type in gridinfo.sites.items():
if site_type == 'RAMBFIFO36E1':
found = True
break
if found:
bram36_site_name = site_name
for site_name, site_type in gridinfo.sites.items():
if site_type == 'RAMB18E1':
bram18_site_name = site_name
if site_type == 'FIFO18E1':
fifo18_site_name = site_name
yield tile_name, bram36_site_name, bram18_site_name, fifo18_site_name
RAM_EXTENSION_OPTS = [ RAM_EXTENSION_OPTS = [
@ -30,69 +49,148 @@ RAM_EXTENSION_OPTS = [
def main(): def main():
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
print(''' print('''
module top(); module top();
''') ''')
params = [] params = []
for tile_name, site_name in gen_bram36(): for tile_name, bram36_site_name, bram18_site_name, fifo18_site_name in gen_bram36(
ram_extension_a = random.choice(RAM_EXTENSION_OPTS) grid):
ram_extension_b = random.choice(RAM_EXTENSION_OPTS) if random.random() < .8:
en_ecc_read = random.randint(0, 1) ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
en_ecc_write = random.randint(0, 1) ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
en_ecc_read = random.randint(0, 1)
en_ecc_write = random.randint(0, 1)
print( print(
''' '''
(* KEEP, DONT_TOUCH, LOC = "{site}" *) (* KEEP, DONT_TOUCH, LOC = "{site}" *)
RAMB36E1 #( RAMB36E1 #(
.READ_WIDTH_A(1), .READ_WIDTH_A(1),
.WRITE_WIDTH_A(1), .WRITE_WIDTH_A(1),
.READ_WIDTH_B(1), .READ_WIDTH_B(1),
.WRITE_WIDTH_B(1), .WRITE_WIDTH_B(1),
.RAM_EXTENSION_A({ram_extension_a}), .RAM_EXTENSION_A({ram_extension_a}),
.RAM_EXTENSION_B({ram_extension_b}), .RAM_EXTENSION_B({ram_extension_b}),
.EN_ECC_READ({en_ecc_read}), .EN_ECC_READ({en_ecc_read}),
.EN_ECC_WRITE({en_ecc_write}) .EN_ECC_WRITE({en_ecc_write})
) bram_{site} ( ) bram_{site} (
.CLKARDCLK(), .CLKARDCLK(),
.CLKBWRCLK(), .CLKBWRCLK(),
.ENARDEN(), .ENARDEN(),
.ENBWREN(), .ENBWREN(),
.REGCEAREGCE(), .REGCEAREGCE(),
.REGCEB(), .REGCEB(),
.RSTRAMARSTRAM(), .RSTRAMARSTRAM(),
.RSTRAMB(), .RSTRAMB(),
.RSTREGARSTREG(), .RSTREGARSTREG(),
.RSTREGB(), .RSTREGB(),
.ADDRARDADDR(), .ADDRARDADDR(),
.ADDRBWRADDR(), .ADDRBWRADDR(),
.DIADI(), .DIADI(),
.DIBDI(), .DIBDI(),
.DIPADIP(), .DIPADIP(),
.DIPBDIP(), .DIPBDIP(),
.WEA(), .WEA(),
.WEBWE(), .WEBWE(),
.DOADO(), .DOADO(),
.DOBDO(), .DOBDO(),
.DOPADOP(), .DOPADOP(),
.DOPBDOP()); .DOPBDOP());
'''.format( '''.format(
site=site_name, site=bram36_site_name,
ram_extension_a=verilog.quote(ram_extension_a), ram_extension_a=verilog.quote(ram_extension_a),
ram_extension_b=verilog.quote(ram_extension_b), ram_extension_b=verilog.quote(ram_extension_b),
en_ecc_read=en_ecc_read, en_ecc_read=en_ecc_read,
en_ecc_write=en_ecc_write, en_ecc_write=en_ecc_write,
)) ))
params.append( params.append(
{ {
'tile': tile_name, 'tile': tile_name,
'site': site_name, 'BRAM36_IN_USE': True,
'RAM_EXTENSION_A': ram_extension_a, 'site': bram36_site_name,
'RAM_EXTENSION_B': ram_extension_b, 'RAM_EXTENSION_A': ram_extension_a,
'EN_ECC_READ': en_ecc_read, 'RAM_EXTENSION_B': ram_extension_b,
'EN_ECC_WRITE': en_ecc_write, 'EN_ECC_READ': en_ecc_read,
}) 'EN_ECC_WRITE': en_ecc_write,
})
else:
print(
'''
(* KEEP, DONT_TOUCH, LOC = "{bram18}" *)
RAMB18E1 #(
.READ_WIDTH_A(1),
.WRITE_WIDTH_A(1),
.READ_WIDTH_B(1),
.WRITE_WIDTH_B(1)
) bram_{bram18} (
.CLKARDCLK(),
.CLKBWRCLK(),
.ENARDEN(),
.ENBWREN(),
.REGCEAREGCE(),
.REGCEB(),
.RSTRAMARSTRAM(),
.RSTRAMB(),
.RSTREGARSTREG(),
.RSTREGB(),
.ADDRARDADDR(),
.ADDRBWRADDR(),
.DIADI(),
.DIBDI(),
.DIPADIP(),
.DIPBDIP(),
.WEA(),
.WEBWE(),
.DOADO(),
.DOBDO(),
.DOPADOP(),
.DOPBDOP());
(* KEEP, DONT_TOUCH, LOC = "{fifo18}" *)
RAMB18E1 #(
.READ_WIDTH_A(1),
.WRITE_WIDTH_A(1),
.READ_WIDTH_B(1),
.WRITE_WIDTH_B(1)
) bram_{fifo18} (
.CLKARDCLK(),
.CLKBWRCLK(),
.ENARDEN(),
.ENBWREN(),
.REGCEAREGCE(),
.REGCEB(),
.RSTRAMARSTRAM(),
.RSTRAMB(),
.RSTREGARSTREG(),
.RSTREGB(),
.ADDRARDADDR(),
.ADDRBWRADDR(),
.DIADI(),
.DIBDI(),
.DIPADIP(),
.DIPBDIP(),
.WEA(),
.WEBWE(),
.DOADO(),
.DOBDO(),
.DOPADOP(),
.DOPBDOP());
'''.format(
bram18=bram18_site_name,
fifo18=fifo18_site_name,
))
params.append(
{
'tile': tile_name,
'BRAM36_IN_USE': False,
'site': bram36_site_name,
})
print("endmodule") print("endmodule")