mirror of https://github.com/openXC7/prjxray.git
Add BRAM36_IN_USE feature.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
34043d1b3d
commit
0deee961eb
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@ -7,7 +7,7 @@
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# SPDX-License-Identifier: ISC
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# read/write width is relatively slow to resolve
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# Even slower with multi bit masks...
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N ?= 2
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N ?= 10
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include ../fuzzer.mk
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@ -21,7 +21,7 @@ def write_ram_ext_tags(segmk, tile_param):
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segmk.add_site_tag(
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tile_param['site'], "{}_{}".format(param, opt), set_val == opt)
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segmk.add_site_tag(
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tile_param['site'], "{}_NONE_OR_UPPER".format(param, opt),
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tile_param['site'], "{}_NONE_OR_UPPER".format(param),
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set_val != "LOWER")
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@ -33,12 +33,16 @@ def main():
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params = json.load(f)
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for tile_param in params:
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write_ram_ext_tags(segmk, tile_param)
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if tile_param['BRAM36_IN_USE']:
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write_ram_ext_tags(segmk, tile_param)
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segmk.add_site_tag(
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tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ'])
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segmk.add_site_tag(
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tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE'])
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segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 1)
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segmk.add_site_tag(
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tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ'])
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segmk.add_site_tag(
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tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE'])
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else:
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segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 0)
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segmk.compile()
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segmk.write()
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@ -12,14 +12,33 @@ import os
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import random
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import json
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray.db import Database
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from prjxray import util
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from prjxray import verilog
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def gen_bram36():
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for tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMBFIFO36E1']):
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yield tile_name, site_name
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def gen_bram36(grid):
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for tile_name in grid.tiles():
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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found = False
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for site_name, site_type in gridinfo.sites.items():
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if site_type == 'RAMBFIFO36E1':
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found = True
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break
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if found:
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bram36_site_name = site_name
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for site_name, site_type in gridinfo.sites.items():
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if site_type == 'RAMB18E1':
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bram18_site_name = site_name
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if site_type == 'FIFO18E1':
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fifo18_site_name = site_name
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yield tile_name, bram36_site_name, bram18_site_name, fifo18_site_name
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RAM_EXTENSION_OPTS = [
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@ -30,69 +49,148 @@ RAM_EXTENSION_OPTS = [
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def main():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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print('''
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module top();
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''')
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params = []
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for tile_name, site_name in gen_bram36():
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ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
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ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
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en_ecc_read = random.randint(0, 1)
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en_ecc_write = random.randint(0, 1)
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for tile_name, bram36_site_name, bram18_site_name, fifo18_site_name in gen_bram36(
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grid):
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if random.random() < .8:
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ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
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ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
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en_ecc_read = random.randint(0, 1)
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en_ecc_write = random.randint(0, 1)
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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RAMB36E1 #(
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.READ_WIDTH_A(1),
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.WRITE_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_B(1),
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.RAM_EXTENSION_A({ram_extension_a}),
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.RAM_EXTENSION_B({ram_extension_b}),
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.EN_ECC_READ({en_ecc_read}),
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.EN_ECC_WRITE({en_ecc_write})
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) bram_{site} (
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.CLKARDCLK(),
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.CLKBWRCLK(),
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.ENARDEN(),
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.ENBWREN(),
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.REGCEAREGCE(),
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.REGCEB(),
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.RSTRAMARSTRAM(),
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.RSTRAMB(),
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.RSTREGARSTREG(),
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.RSTREGB(),
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.ADDRARDADDR(),
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.ADDRBWRADDR(),
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.DIADI(),
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.DIBDI(),
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.DIPADIP(),
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.DIPBDIP(),
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.WEA(),
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.WEBWE(),
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.DOADO(),
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.DOBDO(),
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.DOPADOP(),
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.DOPBDOP());
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'''.format(
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site=site_name,
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ram_extension_a=verilog.quote(ram_extension_a),
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ram_extension_b=verilog.quote(ram_extension_b),
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en_ecc_read=en_ecc_read,
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en_ecc_write=en_ecc_write,
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))
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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RAMB36E1 #(
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.READ_WIDTH_A(1),
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.WRITE_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_B(1),
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.RAM_EXTENSION_A({ram_extension_a}),
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.RAM_EXTENSION_B({ram_extension_b}),
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.EN_ECC_READ({en_ecc_read}),
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.EN_ECC_WRITE({en_ecc_write})
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) bram_{site} (
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.CLKARDCLK(),
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.CLKBWRCLK(),
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.ENARDEN(),
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.ENBWREN(),
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.REGCEAREGCE(),
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.REGCEB(),
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.RSTRAMARSTRAM(),
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.RSTRAMB(),
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.RSTREGARSTREG(),
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.RSTREGB(),
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.ADDRARDADDR(),
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.ADDRBWRADDR(),
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.DIADI(),
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.DIBDI(),
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.DIPADIP(),
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.DIPBDIP(),
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.WEA(),
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.WEBWE(),
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.DOADO(),
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.DOBDO(),
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.DOPADOP(),
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.DOPBDOP());
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'''.format(
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site=bram36_site_name,
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ram_extension_a=verilog.quote(ram_extension_a),
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ram_extension_b=verilog.quote(ram_extension_b),
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en_ecc_read=en_ecc_read,
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en_ecc_write=en_ecc_write,
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))
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params.append(
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{
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'tile': tile_name,
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'site': site_name,
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'RAM_EXTENSION_A': ram_extension_a,
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'RAM_EXTENSION_B': ram_extension_b,
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'EN_ECC_READ': en_ecc_read,
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'EN_ECC_WRITE': en_ecc_write,
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})
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params.append(
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{
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'tile': tile_name,
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'BRAM36_IN_USE': True,
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'site': bram36_site_name,
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'RAM_EXTENSION_A': ram_extension_a,
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'RAM_EXTENSION_B': ram_extension_b,
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'EN_ECC_READ': en_ecc_read,
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'EN_ECC_WRITE': en_ecc_write,
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})
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else:
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{bram18}" *)
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RAMB18E1 #(
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.READ_WIDTH_A(1),
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.WRITE_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_B(1)
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) bram_{bram18} (
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.CLKARDCLK(),
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.CLKBWRCLK(),
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.ENARDEN(),
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.ENBWREN(),
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.REGCEAREGCE(),
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.REGCEB(),
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.RSTRAMARSTRAM(),
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.RSTRAMB(),
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.RSTREGARSTREG(),
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.RSTREGB(),
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.ADDRARDADDR(),
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.ADDRBWRADDR(),
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.DIADI(),
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.DIBDI(),
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.DIPADIP(),
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.DIPBDIP(),
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.WEA(),
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.WEBWE(),
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.DOADO(),
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.DOBDO(),
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.DOPADOP(),
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.DOPBDOP());
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(* KEEP, DONT_TOUCH, LOC = "{fifo18}" *)
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RAMB18E1 #(
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.READ_WIDTH_A(1),
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.WRITE_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_B(1)
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) bram_{fifo18} (
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.CLKARDCLK(),
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.CLKBWRCLK(),
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.ENARDEN(),
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.ENBWREN(),
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.REGCEAREGCE(),
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.REGCEB(),
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.RSTRAMARSTRAM(),
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.RSTRAMB(),
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.RSTREGARSTREG(),
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.RSTREGB(),
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.ADDRARDADDR(),
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.ADDRBWRADDR(),
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.DIADI(),
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.DIBDI(),
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.DIPADIP(),
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.DIPBDIP(),
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.WEA(),
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.WEBWE(),
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.DOADO(),
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.DOBDO(),
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.DOPADOP(),
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.DOPBDOP());
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'''.format(
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bram18=bram18_site_name,
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fifo18=fifo18_site_name,
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))
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params.append(
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{
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'tile': tile_name,
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'BRAM36_IN_USE': False,
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'site': bram36_site_name,
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})
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print("endmodule")
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