mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1006 from litghost/move_ilogic_and_ologic_to_ioi3
Move ILOGIC and OLOGIC to IOI3 tiles for consistency.
This commit is contained in:
litghost
GitHub
commit
ae80db55ad
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@ -1,20 +1,28 @@
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N := 30
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include ../fuzzer.mk
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database: build/segbits_xiob33.db
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database: build/segbits_xioi3.db
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build/segbits_xiob33.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 6 -o build/segbits_xiob33.rdb $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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build/segbits_xioi3.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 6 -o build/segbits_xioi3.rdb $$(find -name segdata_*)
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build/segbits_xiob33.db: build/segbits_xiob33.rdb
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build/segbits_xioi3.db: build/segbits_xioi3.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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${XRAY_MASKMERGE} build/mask_xioi3.db $$(find -name segdata_*)
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pushdb:
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${XRAY_MERGEDB} liob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} riob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db
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${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db
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${XRAY_MERGEDB} lioi3 build/segbits_xioi3.db
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${XRAY_MERGEDB} lioi3_tbytesrc build/segbits_xioi3.db
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${XRAY_MERGEDB} lioi3_tbyteterm build/segbits_xioi3.db
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${XRAY_MERGEDB} rioi3 build/segbits_xioi3.db
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${XRAY_MERGEDB} rioi3_tbytesrc build/segbits_xioi3.db
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${XRAY_MERGEDB} rioi3_tbyteterm build/segbits_xioi3.db
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${XRAY_MERGEDB} mask_lioi3 build/mask_xioi3.db
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${XRAY_MERGEDB} mask_lioi3_tbytesrc build/mask_xioi3.db
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${XRAY_MERGEDB} mask_lioi3_tbyteterm build/mask_xioi3.db
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${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db
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${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db
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${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db
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.PHONY: database pushdb
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@ -19,6 +19,8 @@ def handle_data_width(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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site = d['ilogic_loc']
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# It appears several widths end up with the same bitstream pattern.
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# This groups those widths together for documentation.
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widths = [
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@ -40,31 +42,30 @@ def handle_data_width(segmk, d):
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zero_opt = 2
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W_OPT_ZERO = width_map[zero_opt]
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if d['DATA_WIDTH'] == zero_opt:
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segmk.add_site_tag(
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d['site'], 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 1)
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segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 1)
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for opt in width_map.values():
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if opt == W_OPT_ZERO:
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continue
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segmk.add_site_tag(
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d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt), 0)
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segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(opt), 0)
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else:
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w_opt = width_map[d['DATA_WIDTH']]
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if w_opt != W_OPT_ZERO:
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segmk.add_site_tag(
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d['site'], 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 0)
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segmk.add_site_tag(
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d['site'], 'ISERDES.DATA_WIDTH.{}'.format(w_opt), 1)
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site, 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 0)
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segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(w_opt), 1)
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def handle_data_rate(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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site = d['ilogic_loc']
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for opt in ['SDR', 'DDR']:
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segmk.add_site_tag(
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d['site'], 'ISERDES.DATA_RATE.{}'.format(opt),
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site, 'ISERDES.DATA_RATE.{}'.format(opt),
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verilog.unquote(d['DATA_RATE']) == opt)
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@ -76,7 +77,7 @@ def main():
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design = json.load(f)
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for d in design:
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site = d['site']
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site = d['ilogic_loc']
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handle_data_width(segmk, d)
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handle_data_rate(segmk, d)
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@ -1,20 +1,28 @@
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N := 40
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include ../fuzzer.mk
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database: build/segbits_xiob33.db
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database: build/segbits_xioi3.db
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build/segbits_xiob33.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 6 -o build/segbits_xiob33.rdb $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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build/segbits_xioi3.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 6 -o build/segbits_xioi3.rdb $$(find -name segdata_*)
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build/segbits_xiob33.db: build/segbits_xiob33.rdb
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build/segbits_xioi3.db: build/segbits_xioi3.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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${XRAY_MASKMERGE} build/mask_xioi3.db $$(find -name segdata_*)
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pushdb:
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${XRAY_MERGEDB} liob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} riob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db
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${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db
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${XRAY_MERGEDB} lioi3 build/segbits_xioi3.db
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${XRAY_MERGEDB} lioi3_tbytesrc build/segbits_xioi3.db
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${XRAY_MERGEDB} lioi3_tbyteterm build/segbits_xioi3.db
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${XRAY_MERGEDB} rioi3 build/segbits_xioi3.db
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${XRAY_MERGEDB} rioi3_tbytesrc build/segbits_xioi3.db
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${XRAY_MERGEDB} rioi3_tbyteterm build/segbits_xioi3.db
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${XRAY_MERGEDB} mask_lioi3 build/mask_xioi3.db
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${XRAY_MERGEDB} mask_lioi3_tbytesrc build/mask_xioi3.db
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${XRAY_MERGEDB} mask_lioi3_tbyteterm build/mask_xioi3.db
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${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db
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${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db
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${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db
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.PHONY: database pushdb
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@ -19,23 +19,25 @@ def handle_data_width(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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site = d['ologic_loc']
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for opt in [2, 3, 4, 5, 6, 7, 8]:
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segmk.add_site_tag(
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d['site'], 'OSERDESE.DATA_WIDTH.W{}'.format(opt),
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site, 'OSERDESE.DATA_WIDTH.W{}'.format(opt),
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d['DATA_WIDTH'] == opt)
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if verilog.unquote(d['DATA_RATE_OQ']) == 'DDR':
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# DDR + WIDTH 6/8 have some overlapping bits, create a feature.
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OVERLAPPING_WIDTHS = [6, 8]
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segmk.add_site_tag(
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d['site'], 'OSERDESE.DATA_WIDTH.DDR.W{}'.format(
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site, 'OSERDESE.DATA_WIDTH.DDR.W{}'.format(
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'_'.join(map(str, OVERLAPPING_WIDTHS))),
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d['DATA_WIDTH'] in OVERLAPPING_WIDTHS)
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else:
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# SDR + WIDTH 2/4/5/6 have some overlapping bits, create a feature.
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OVERLAPPING_WIDTHS = [2, 4, 5, 6]
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segmk.add_site_tag(
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d['site'], 'OSERDESE.DATA_WIDTH.SDR.W{}'.format(
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site, 'OSERDESE.DATA_WIDTH.SDR.W{}'.format(
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'_'.join(map(str, OVERLAPPING_WIDTHS))),
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d['DATA_WIDTH'] in OVERLAPPING_WIDTHS)
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@ -48,7 +50,7 @@ def main():
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design = json.load(f)
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for d in design:
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site = d['site']
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site = d['ologic_loc']
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handle_data_width(segmk, d)
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